公开(公告)号：US08431968B2

公开(公告)日：2013-04-30

申请号：US12845162

申请日：2010-07-28

申请人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Shen-Feng Chen ,  Meng-Fu You

发明人： Lee-Chung Lu ,  Wen-Hao Chen ,  Yuan-Te Hou ,  Shen-Feng Chen ,  Meng-Fu You

IPC分类号： H01L23/52

CPC分类号： G06F17/5077 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01L23/5286 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

公开(公告)号：US08327301B2

公开(公告)日：2012-12-04

申请号：US12616956

申请日：2009-11-12

申请人： Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

发明人： Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

IPC分类号： G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/00 ,  G03F7/70433 ,  G03F7/705 ,  G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： In a method of designing a double patterning mask set, a chip is first divided into a grid that includes grid cells. A metal layer of the chip is laid out. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first indicator, and all right-boundary patterns of the metal layer are assigned with a second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set. All patterns assigned with the first indicator are transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set.

摘要翻译： 在设计双重图案掩模组的方法中，首先将芯片划分成包括网格单元的网格。 布置芯片的金属层。 在基本上每个网格单元中，金属层的所有左边界图案被分配有第一指示符，并且金属层的所有右边界图案被分配有第二指示符。 从一行中的一个网格单元开始，指示符更改在整行中传播。 网格单元中的所有图案都转移到双重图案掩模集合。 分配有第一指示符的所有图案被转移到双重图案掩模组的第一掩模，并且分配有第二指示符的所有图案被转移到双重图案掩模组的第二掩模。

公开(公告)号：US08214773B2

公开(公告)日：2012-07-03

申请号：US12617470

申请日：2009-11-12

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai

IPC分类号： G06F17/50

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  G03F1/78 ,  H01J37/3174

摘要： A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system.

摘要翻译： 一种形成用于晶片的集成电路的方法包括提供电子束直接写入（EBDW）系统。 为晶片生成栅格，其中栅格包括栅格线。 为晶片布置了集成电路，其中集成电路中的基本上没有敏感特征跨越电网的栅格线。 使用EBDW系统在晶片上执行EBDW。

公开(公告)号：US08119310B1

公开(公告)日：2012-02-21

申请号：US12872938

申请日：2010-08-31

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

IPC分类号： G03F9/00 ,  G06F17/50

CPC分类号： G03F1/70

摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

摘要翻译： 一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模 。 确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。 对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

公开(公告)号：US20110035717A1

公开(公告)日：2011-02-10

申请号：US12846594

申请日：2010-07-29

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu Alex Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

摘要翻译： 本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。 计算机程序产品具有其上体现计算机程序的介质。 此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和 收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

公开(公告)号：US20100199238A1

公开(公告)日：2010-08-05

申请号：US12617046

申请日：2009-11-12

申请人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

发明人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

摘要翻译： 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

公开(公告)号：US09672315B2

公开(公告)日：2017-06-06

申请号：US12846594

申请日：2010-07-29

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

公开(公告)号：US08286119B2

公开(公告)日：2012-10-09

申请号：US12617046

申请日：2009-11-12

申请人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

发明人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

摘要翻译： 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

公开(公告)号：US08245174B2

公开(公告)日：2012-08-14

申请号：US12549087

申请日：2009-08-27

申请人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

摘要翻译： 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

公开(公告)号：US20110023002A1

公开(公告)日：2011-01-27

申请号：US12549087

申请日：2009-08-27

申请人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

摘要翻译： 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。