公开(公告)号：US06960811B2

公开(公告)日：2005-11-01

申请号：US10929735

申请日：2004-08-30

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0266

摘要： A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

摘要翻译： 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及所述第一和第二晶体管以及所述阱中的所述第二导电类型的掺杂区域，其中所述第一和第二晶体管中的每一个的漏极和源极区域的轮廓是不对称的，并且所述漏极区域的面积为 小于第一和第二晶体管中的每一个中的源极区域。

公开(公告)号：US20050180071A1

公开(公告)日：2005-08-18

申请号：US10779341

申请日：2004-02-13

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0288

摘要： A circuit and a method for ESD protection are disclosed. The circuit includes an ESD protection circuit coupled to a pad. A device is coupled to the pad and an internal circuit. The device generates a voltage drop between the pad and the internal circuit, protecting thin oxide layers of the internal circuit from damage. The method comprises coupling an internal circuit to an ESD protection circuit and generating a voltage drop between a pad and the internal circuit to protect thin oxide layers of the internal circuit from damage when an ESD pulse is coupled to the pad.

摘要翻译： 公开了一种用于ESD保护的电路和方法。 电路包括耦合到焊盘的ESD保护电路。 器件耦合到焊盘和内部电路。 该器件在焊盘和内部电路之间产生电压降，保护内部电路的薄氧化物层免受损坏。 该方法包括将内部电路耦合到ESD保护电路并且在衬垫和内部电路之间产生电压降，以在ESD脉冲耦合到衬垫时保护内部电路的薄氧化物层免受损坏。

公开(公告)号：US20050176195A1

公开(公告)日：2005-08-11

申请号：US11072014

申请日：2005-03-04

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

公开(公告)号：US20050041346A1

公开(公告)日：2005-02-24

申请号：US10644718

申请日：2003-08-20

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0285

摘要： A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

摘要翻译： 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US06730968B1

公开(公告)日：2004-05-04

申请号：US10205520

申请日：2002-07-25

申请人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L2362

CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

摘要翻译： 本发明提供了用于整个芯片静电放电，ESD保护方案的两个电路实施例。 它还包括一种全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06614078B2

公开(公告)日：2003-09-02

申请号：US10147272

申请日：2002-05-16

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921

摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

申请人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

发明人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

摘要翻译： 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

公开(公告)号：US06420221B1

公开(公告)日：2002-07-16

申请号：US09507646

申请日：2000-02-22

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

IPC分类号： H01L218238

CPC分类号： H01L21/823878 ,  H01L27/0921

摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

摘要翻译： 通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。 连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。 在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。 与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。 在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

公开(公告)号：US5903499A

公开(公告)日：1999-05-11

申请号：US928227

申请日：1997-09-12

申请人： Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

发明人： Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.

摘要翻译： 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。 同时，向控制栅极施加第一相对较大的负电压。 同时对半导体衬底施加接地参考电位。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加第二相对大的负电压脉冲。

公开(公告)号：US5838618A

公开(公告)日：1998-11-17

申请号：US927472

申请日：1997-09-11

申请人： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/14

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.

摘要翻译： 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。 通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。 同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。 擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。 源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。