公开(公告)号：US20150194373A1

公开(公告)日：2015-07-09

申请号：US14151110

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer ,  Jürgen Schredl ,  Xaver Schlögel ,  Klaus Schiess

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract translation: 半导体封装装置包括晶体管器件，其包括包括源电极和栅电极的第一侧，具有第一表面的管芯焊盘和具有第一表面的引线。 第一导电构件设置在源电极和管芯焊盘的第一表面之间，并将源极与管芯焊盘的第一表面隔开一定距离，该距离大于栅电极与第一表面之间的距离 铅。

公开(公告)号：US08952545B2

公开(公告)日：2015-02-10

申请号：US13965630

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Henrik Ewe ,  Klaus Schiess ,  Manfred Mengel

IPC: H01L23/48 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer.

Abstract translation: 一个方面是包括载体的器件，其包括第一导电层，在第一导电层上的第一绝缘层，以及从第一绝缘层的第一面到第一绝缘层的第二面的至少一个第一通孔连接 。 半导体芯片附着到载体上，第二绝缘层位于载体和半导体芯片之上。 金属层在第二绝缘层之上。 第二直通连接通过第二绝缘层将半导体芯片电耦合到金属层。 第三直通连接是通过第二绝缘层将载体电耦合到金属层。