公开(公告)号：US10903364B2

公开(公告)日：2021-01-26

申请号：US16304620

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sanaz K. Gardner ,  Chandra S. Mohapatra ,  Matthew V. Metz ,  Gilbert Dewey ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/775 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.

公开(公告)号：US10892337B2

公开(公告)日：2021-01-12

申请号：US16327198

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Karthik Jambunathan ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Patrick Morrow ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L23/485

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

公开(公告)号：US10818793B2

公开(公告)日：2020-10-27

申请号：US16283756

申请日：2019-02-23

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/775 ,  H01L29/12 ,  H01L27/088 ,  H01L29/205 ,  H01L21/02

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US10651288B2

公开(公告)日：2020-05-12

申请号：US15575810

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/762 ,  H01L29/775 ,  H01L29/20 ,  H01L21/02 ,  H01L29/205 ,  B82Y10/00 ,  H01L21/306

Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

公开(公告)号：US10586848B2

公开(公告)日：2020-03-10

申请号：US16071894

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/306 ,  H01L21/764 ,  H01L29/08 ,  H01L29/20 ,  H01L29/78

Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.

公开(公告)号：US10446685B2

公开(公告)日：2019-10-15

申请号：US15755489

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Matthew V. Metz ,  Harold W. Kennel ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L27/092 ,  H01L29/778

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

公开(公告)号：US10431690B2

公开(公告)日：2019-10-01

申请号：US15575111

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Sanaz K. Gardner

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

公开(公告)号：US10418464B2

公开(公告)日：2019-09-17

申请号：US15573168

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Hei Kam ,  Tahir Ghani ,  Karthik Jambunathan ,  Chandra S. Mohapatra

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8256 ,  H01L29/08 ,  H01L21/8258 ,  H01L27/06

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

公开(公告)号：US10388764B2

公开(公告)日：2019-08-20

申请号：US15755448

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/02 ,  H01L27/092 ,  H01L29/778 ,  H01L29/78

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.

公开(公告)号：US10211208B2

公开(公告)日：2019-02-19

申请号：US15574820

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew V. Metz ,  Anand S. Murthy ,  Tahir Ghani ,  Willy Rachmady ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Glenn A. Glass

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8258

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.