公开(公告)号：US11482621B2

公开(公告)日：2022-10-25

申请号：US16143222

申请日：2018-09-26

申请人： Intel Corporation

发明人： Willy Rachmady ,  Patrick Morrow ,  Aaron Lilak ,  Rishabh Mehandru ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Kimin Jun ,  Ryan Keech ,  Anh Phan ,  Ehren Mannebach

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06

摘要： Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20220328663A1

公开(公告)日：2022-10-13

申请号：US17853036

申请日：2022-06-29

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

公开(公告)号：US11380684B2

公开(公告)日：2022-07-05

申请号：US16145817

申请日：2018-09-28

申请人： INTEL CORPORATION

发明人： Gilbert Dewey ,  Aaron Lilak ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Abhishek Sharma ,  Patrick Morrow ,  Hui Jae Yoo

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

摘要： Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

公开(公告)号：US11296203B2

公开(公告)日：2022-04-05

申请号：US16649183

申请日：2017-12-26

申请人： Intel Corporation

发明人： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC分类号： H01L29/51 ,  H01L21/285 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

摘要： An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.

公开(公告)号：US11244943B2

公开(公告)日：2022-02-08

申请号：US16728983

申请日：2019-12-27

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC分类号： H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11171207B2

公开(公告)日：2021-11-09

申请号：US16647695

申请日：2017-12-20

申请人： INTEL CORPORATION

发明人： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210202319A1

公开(公告)日：2021-07-01

申请号：US16728903

申请日：2019-12-27

申请人： Intel Corporation

发明人： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC分类号： H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US20200295003A1

公开(公告)日：2020-09-17

申请号：US16354960

申请日：2019-03-15

申请人： INTEL CORPORATION

发明人： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

摘要： Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US20200279916A1

公开(公告)日：2020-09-03

申请号：US16647695

申请日：2017-12-20

申请人： INTEL CORPORATION

发明人： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66

摘要： A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20200168724A1

公开(公告)日：2020-05-28

申请号：US16632266

申请日：2017-08-18

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.