公开(公告)号：US11310907B2

公开(公告)日：2022-04-19

申请号：US16697699

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11302618B2

公开(公告)日：2022-04-12

申请号：US15948803

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff ,  Thomas Sounart ,  Johanna M. Swan

IPC: H01G4/00 ,  H01L23/498 ,  H01G4/008 ,  H05K1/16 ,  H01G4/30 ,  H01L21/48 ,  H05K1/18 ,  H01L41/047 ,  H01G4/12 ,  H01L41/187 ,  H01L41/053 ,  H01L41/29 ,  H01L41/314 ,  H01L29/16 ,  H01L23/14 ,  H01L23/00 ,  H05K1/11 ,  H01L23/367 ,  H01L41/09 ,  H01L41/113

Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.

公开(公告)号：US20220093547A1

公开(公告)日：2022-03-24

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11233015B2

公开(公告)日：2022-01-25

申请号：US16638741

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid

IPC: H01L23/00 ,  B33Y80/00 ,  H01L21/50 ,  H01L23/16

Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.

公开(公告)号：US11227825B2

公开(公告)日：2022-01-18

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/03 ,  H05K1/16 ,  H01F17/00 ,  H01F17/06 ,  H01L21/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/60 ,  G11B5/17 ,  G11B5/31 ,  G11B5/147 ,  G11B5/187 ,  H01L23/498 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20210407877A1

公开(公告)日：2021-12-30

申请号：US16911820

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Paul Diglio

IPC: H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L21/56

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

公开(公告)号：US11189580B2

公开(公告)日：2021-11-30

申请号：US16721327

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H05K1/18 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20210193597A1

公开(公告)日：2021-06-24

申请号：US16721603

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/498 ,  H01L21/48 ,  H01H61/01 ,  H01H49/00

Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.

公开(公告)号：US11016288B2

公开(公告)日：2021-05-25

申请号：US16072161

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Feras Eid ,  Johanna M. Swan ,  Thomas L. Sounart ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B26/08 ,  H01L27/20 ,  H01L41/09 ,  H01L41/253

Abstract: Embodiments of the invention include a display formed on an organic substrate and methods of forming such a device. According to an embodiment, an array of pixel mirrors may be formed on the organic substrate. For example, each of the pixel mirrors is actuatable about one or more axes out of the plane of the organic substrate. Additionally, embodiments of the invention may include an array of routing mirrors formed on the organic substrate. According to an embodiment, each of the routing mirrors is actuatable about two axes out of the plane of the organic substrate. In embodiments of the invention, a light source may be used for emitting light towards the array of routing mirrors. For example, light emitted from the light source may be reflected to one or more of the pixel mirrors by one of the routing mirrors.

公开(公告)号：US20210143111A1

公开(公告)日：2021-05-13

申请号：US16683125

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/00 ,  H01L23/053

Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.