公开(公告)号：US11456281B2

公开(公告)日：2022-09-27

申请号：US16147742

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Yí Li ,  Zhiguo Qian ,  Prasad Ramanathan ,  Saikumar Jayaraman ,  Kemal Aygun ,  Hector Amador ,  Andrew Collins ,  Jianyong Xie ,  Shigeki Tomishima

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/00

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

公开(公告)号：US11437366B2

公开(公告)日：2022-09-06

申请号：US16643553

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Kemal Aygun ,  Yidnekachew S. Mekonnen

IPC: H01L23/525 ,  H01L27/06 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L23/00

Abstract: Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.

公开(公告)号：US20220130763A1

公开(公告)日：2022-04-28

申请号：US17572167

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US11295998B2

公开(公告)日：2022-04-05

申请号：US15945641

申请日：2018-04-04

Applicant: Intel Corporation

Inventor： Stephen Christianson ,  Stephen Hall ,  Emile Davies-Venn ,  Dong-Ho Han ,  Kemal Aygun ,  Konika Ganguly ,  Jun Liao ,  M. Reza Zamani ,  Cory Mason ,  Kirankumar Kamisetty

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01P3/08 ,  H01L21/48 ,  H01P11/00

Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

公开(公告)号：US20210352807A1

公开(公告)日：2021-11-11

申请号：US17383084

申请日：2021-07-22

Applicant: INTEL CORPORATION

Inventor： Eric Li ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

IPC: H05K3/00 ,  H05K3/02 ,  H05K1/02

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

公开(公告)号：US20210296240A1

公开(公告)日：2021-09-23

申请号：US16319647

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen ,  Dae-Woo Kim ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L21/48

Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.

公开(公告)号：US11089689B2

公开(公告)日：2021-08-10

申请号：US16081487

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Eric Li ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

IPC: H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/46

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.

公开(公告)号：US20210057345A1

公开(公告)日：2021-02-25

申请号：US17091657

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

公开(公告)号：US10910314B2

公开(公告)日：2021-02-02

申请号：US16712091

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Joseph Chen ,  Emile Davies-Venn ,  Kemal Aygun ,  Mitul B. Modi

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L21/48 ,  H01L23/66

Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.

公开(公告)号：US10854539B2

公开(公告)日：2020-12-01

申请号：US16509387

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.