公开(公告)号：US11903138B2

公开(公告)日：2024-02-13

申请号：US17383084

申请日：2021-07-22

Applicant: INTEL CORPORATION

Inventor： Eric Li ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/46

CPC classification number: H05K3/0026 ,  H05K1/0228 ,  H05K3/027 ,  H05K3/4694 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2203/107 ,  H05K2203/1476

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

公开(公告)号：US10128591B2

公开(公告)日：2018-11-13

申请号：US14847482

申请日：2015-09-08

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Kai Xiao ,  Lu-Vong T. Phan

IPC: H01R29/00 ,  H01R13/71 ,  H01R12/70 ,  H01R12/71 ,  H01R13/703 ,  H01R24/60

Abstract: One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.

公开(公告)号：US20170086288A1

公开(公告)日：2017-03-23

申请号：US14862159

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Shaowu Huang ,  Kai Xiao

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H01P3/08 ,  H01P11/00

CPC classification number: H01P3/081 ,  H01P3/04 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09036 ,  H05K2201/09872

Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.

公开(公告)号：US20160276091A1

公开(公告)日：2016-09-22

申请号：US14664827

申请日：2015-03-21

Applicant: INTEL CORPORATION

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC: H01F27/28 ,  H05K3/30 ,  H05K1/11 ,  H01F41/04 ,  H05K1/18

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/165

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US20190098764A1

公开(公告)日：2019-03-28

申请号：US16081487

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： ERIC LI ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/02

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.

公开(公告)号：US09894752B2

公开(公告)日：2018-02-13

申请号：US14678714

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

IPC: H01F27/28 ,  H01F41/04 ,  H05K1/02 ,  H05K1/16 ,  H01F17/00 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01F17/0013 ,  H01F2017/002 ,  H05K1/0233 ,  H05K1/116 ,  H05K1/165

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

公开(公告)号：US09338882B2

公开(公告)日：2016-05-10

申请号：US14278330

申请日：2014-05-15

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08 ,  H01P11/00 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

公开(公告)号：US09935036B2

公开(公告)日：2018-04-03

申请号：US15036385

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Beom-Taek Lee

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/07 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2224/85399

Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.

公开(公告)号：US20170168528A1

公开(公告)日：2017-06-15

申请号：US14968698

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Gong Ouyang ,  Kai Xiao ,  Lu-Vong Phan

IPC: G06F1/18 ,  G06F1/16

CPC classification number: G06F1/185 ,  G06F1/1616 ,  G06F1/1637 ,  G06F1/1681 ,  H05K1/029 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/10159 ,  Y02P70/611

Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.

公开(公告)号：US09318850B2

公开(公告)日：2016-04-19

申请号：US14286494

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Xiang Li ,  Hao-Han Hsu ,  Yun Ling ,  Gong Ouyang ,  Kai Xiao ,  Jiangqi He ,  Lu-Vong T. Phan ,  Wei Xu

IPC: H01R12/00 ,  H01R13/6598 ,  H01R12/72 ,  H05K3/28 ,  H05K3/36 ,  H01R43/18

CPC classification number: H01R13/6598 ,  H01R12/712 ,  H01R12/721 ,  H01R12/724 ,  H01R13/658 ,  H01R43/18 ,  H05K3/284 ,  H05K3/36 ,  Y10T29/49128

Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，诸如边缘连接器的连接器包括连接器壳体，构造在壳体内的第一组引脚，并且具有耦合到第一电路板的相应信号线的第一端和第二端耦合到相应的信号线 第二电路板的配合连接器以及适于壳体的导电材料，以减少由一个或多个干扰源造成的干扰。 描述和要求保护其他实施例。