公开(公告)号：US11610856B2

公开(公告)日：2023-03-21

申请号：US16449923

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.

公开(公告)号：US11581287B2

公开(公告)日：2023-02-14

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Sanka Ganesan ,  Bernd Waidhas ,  Thomas Wagner ,  Lizabeth Keser

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US10765046B2

公开(公告)日：2020-09-01

申请号：US16290448

申请日：2019-03-01

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.

公开(公告)号：US10601426B1

公开(公告)日：2020-03-24

申请号：US16123765

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/177 ,  H03K19/1776 ,  H01L25/18 ,  H01L23/367

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US09918414B2

公开(公告)日：2018-03-13

申请号：US14974222

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

CPC classification number: H05K9/0007 ,  H01L23/552 ,  H01L2224/97 ,  H05K9/006 ,  H05K9/0086

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.