公开(公告)号：US12206410B2

公开(公告)日：2025-01-21

申请号：US18169988

申请日：2023-02-16

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L23/367 ,  H01L25/18

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US11652020B2

公开(公告)日：2023-05-16

申请号：US16425264

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Robert Sankman

IPC: H05K1/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H05K1/14 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/42 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H05K1/144 ,  H05K1/181 ,  H01L2224/16227 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2201/10424

Abstract: Integrated circuit assemblies, electronic systems, and methods for fabricating the same are disclosed. An integrated circuit assembly is formed by thermally contacting at least two integrated circuit packages to opposite sides of a shared heat dissipation device. In one embodiment, the at least two integrated circuit packages are electrically attached to an electronic card to form an intermediate integrated circuit assembly. In a further embodiment, the integrated circuit assembly includes at least one intermediate integrated circuit assembly electrically attached to an electronic board.

公开(公告)号：US20200186149A1

公开(公告)日：2020-06-11

申请号：US16788760

申请日：2020-02-12

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US12148703B2

公开(公告)日：2024-11-19

申请号：US18135067

申请日：2023-04-14

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Robert May

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

公开(公告)号：US11915996B2

公开(公告)日：2024-02-27

申请号：US16407587

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H01L23/427 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/427 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/433 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/16 ,  H01L2224/16225

Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.

公开(公告)号：US20200381330A1

公开(公告)日：2020-12-03

申请号：US16425264

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Robert Sankman

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H05K1/18 ,  H05K1/14

Abstract: An integrated circuit assembly may be formed comprising at least two integrated circuit packages, wherein the at least two integrated circuit packages share a heat dissipation device. In one embodiment, the at least two integrated circuit packages may be electrically attached to an electronic card to form an intermediate integrated circuit assembly. In a further embodiment, the integrated circuit assembly may comprise at least one intermediate integrated circuit assembly electrically attached to an electronic board.

公开(公告)号：US20200006305A1

公开(公告)日：2020-01-02

申请号：US16022511

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Krishna Bharath ,  Beomseok Choi ,  Robert Sankman

IPC: H01L25/18 ,  H01L25/065 ,  H02M1/08

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.

公开(公告)号：US10396046B2

公开(公告)日：2019-08-27

申请号：US15859316

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Robert Sankman

IPC: H01F27/00 ,  H01L23/64 ,  H01L23/00 ,  H01F27/28 ,  H05K1/02

Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.

公开(公告)号：US10264717B2

公开(公告)日：2019-04-16

申请号：US15712413

申请日：2017-09-22

Applicant: INTEL CORPORATION

Inventor： Robert Sankman

IPC: H05K9/00 ,  H01L23/552

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.