公开(公告)号：US09288019B2

公开(公告)日：2016-03-15

申请号：US14324062

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Nicholas P. Cowley ,  Chi Man Kan ,  Ruchir Saraswat

IPC: H04B3/46 ,  H04L1/20 ,  H03D13/00 ,  H04B3/14

CPC classification number: H03K5/13 ,  H03D13/003 ,  H03K2005/00019 ,  H03L7/097 ,  H04B3/146 ,  H04L1/205

Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Abstract translation: 实施例包括用于抖动均衡和相位误差检测的装置，方法和系统。 在实施例中，通信电路可以包括用于传递数据信号和时钟路径以传递时钟信号的数据路径。 抖动均衡器可以与数据路径和/或时钟路径耦合以分别向数据信号和/或时钟信号提供可编程延迟。 可以通过训练处理来确定延迟，其中可以通过调制频率来调制电源电压。 延迟可以取决于电源电压的值，例如电源电压的电压电平和/或抖动频率分量。 还描述了可以与通信电路和/或其他实施例一起使用的相位误差检测器。

公开(公告)号：US09281281B2

公开(公告)日：2016-03-08

申请号：US14195661

申请日：2014-03-03

Applicant: INTEL CORPORATION

Inventor： Nicholas P. Cowley ,  Ruchir Saraswat

IPC: H01L23/552 ,  H01L23/60 ,  H01L23/48 ,  H01L23/13 ,  H01L23/66 ,  H01L21/02

CPC classification number: H01L23/552 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/60 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06534 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed.

公开(公告)号：US20160006544A1

公开(公告)日：2016-01-07

申请号：US14324062

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Nicholas P. Cowley ,  Chi Man Kan ,  Ruchir Saraswat

IPC: H04L1/20 ,  H04B3/14 ,  H03D13/00

CPC classification number: H03K5/13 ,  H03D13/003 ,  H03K2005/00019 ,  H03L7/097 ,  H04B3/146 ,  H04L1/205

Abstract: Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.