公开(公告)号：US11335800B2

公开(公告)日：2022-05-17

申请号：US16016411

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8252

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20220059552A1

公开(公告)日：2022-02-24

申请号：US17001525

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Sumit Ashtekar ,  Rahul Ramaswamy ,  Walid Hafez ,  Hector M. Saavedra Garcia

IPC: H01L27/112 ,  H01H85/02 ,  H01L29/78 ,  H01L29/66

Abstract: A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.

公开(公告)号：US10811751B2

公开(公告)日：2020-10-20

申请号：US16461554

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Chen-Guan Lee

IPC: H01P3/12 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/66 ,  H01P3/127 ,  H01P5/12 ,  H01P11/00

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

公开(公告)号：US09972616B2

公开(公告)日：2018-05-15

申请号：US14909980

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Walid Hafez ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L21/70 ,  H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/775 ,  H01C7/06 ,  H01C17/232

CPC classification number: H01L27/0629 ,  H01C7/06 ,  H01C17/232 ,  H01L28/20 ,  H01L28/24 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

Abstract: Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

公开(公告)号：US20170162693A1

公开(公告)日：2017-06-08

申请号：US15323726

申请日：2014-08-05

Applicant: INTEL CORPORATION

Inventor： Gopinath Bhimarasetti ,  Walid Hafez ,  Joodong Park ,  Weimin Han ,  Raymond Cotner

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7846 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/76202 ,  H01L21/823431 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.