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    Mitigation of EMI/ESD-caused transmission errors on an electronic circuit
    35.
    发明授权
    Mitigation of EMI/ESD-caused transmission errors on an electronic circuit 有权
    EMI / ESD引起的电子电路传输错误的减轻

    公开(公告)号：US09548773B1

    公开(公告)日：2017-01-17

    申请号：US15066194

    申请日：2016-03-10

    申请人： International Business Machines Corporation

    发明人： David D. Cadigan ,  Samuel R. Connor ,  Michael A. Cracraft ,  William V. Huott ,  Adam J. McPadden ,  Anuwat Saetow ,  Gary A. Tressler

    IPC分类号： H04B1/04 ,  H04B17/336

    CPC分类号： H04B1/0475 ,  H04B17/17 ,  H04B17/318 ,  H04B17/336

    摘要： A method detects and mitigates harm caused by electromagnetic interference (EMI) to digital transmissions within an electronic circuit. One or more processors check for an initial transmission error during an initial digital transmission between a digital transmitter and a digital receiver on an electronic circuit. In response to detecting the initial transmission error, the processor(s) receive electromagnetic interference (EMI) detection signals from one or more EMI detectors. In response to determining that the EMI detection signals represent an EMI level that exceeds a predetermined value, the processor(s) identify an EMI anomaly source on the electronic circuit and adjusts the EMI anomaly source until the EMI level has been reduced to a nominal level. A copy of the initial digital transmission is then resent from the digital transmitter to the digital receiver. If no transmission error reoccurs, then the EMI anomaly source is kept in the adjusted state.

    摘要翻译： 一种方法可以检测和减轻由电磁干扰（EMI）引起的对电子电路内的数字传输的危害。 一个或多个处理器在电子电路上的数字发射机和数字接收机之间的初始数字传输期间检查初始传输错误。 响应于检测到初始传输错误，处理器从一个或多个EMI检测器接收电磁干扰（EMI）检测信号。 响应于确定EMI检测信号表示超过预定值的EMI电平，处理器识别电子电路上的EMI异常源并调整EMI异常源，直到EMI电平降低到标称电平 。 然后，将初始数字传输的副本从数字发射机重新发送到数字接收机。 如果没有发生传输错误，则EMI异常源保持在调整状态。

    Implementing simultaneous read and write operations utilizing dual port DRAM
    36.
    发明授权
    Implementing simultaneous read and write operations utilizing dual port DRAM 有权
    使用双端口DRAM实现同时的读写操作

    公开(公告)号：US09305619B2

    公开(公告)日：2016-04-05

    申请号：US14310717

    申请日：2014-06-20

    申请人： International Business Machines Corporation

    发明人： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

    IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C8/16 ,  G06F11/10 ,  G11C29/04

    CPC分类号： G11C7/1075 ,  G06F11/1048 ,  G11C7/1045 ,  G11C8/16 ,  G11C2029/0411 ,  G11C2207/2209

    摘要： A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

    摘要翻译： 提供了一种方法，系统和存储器控制器，用于在利用双端口动态随机存取存储器（DRAM）配置的存储器子系统中实现同时的读和写操作。 DRAM包括第一分区和第二分区。 存储器控制器确定存储器需求是否高于或低于使用阈值。 如果存储器要求低于使用阈值，则存储器被划分为读缓冲器和写缓冲器，其中写入缓冲器并从读缓冲器读取数据，数据从写缓冲器传送到读缓冲器 纠错码（ECC）引擎。 如果内存要求高于使用阈值，则整个内存将用于读取和写入。

    PRIORITIZING REFRESHES IN A MEMORY DEVICE
    37.
    发明申请
    PRIORITIZING REFRESHES IN A MEMORY DEVICE 有权
    在存储设备中优先刷新

    公开(公告)号：US20160027494A1

    公开(公告)日：2016-01-28

    申请号：US14878174

    申请日：2015-10-08

    申请人： International Business Machines Corporation

    发明人： Edgar R. Cordero ,  Joab D. Henderson ,  Kyu-hyoun Kim ,  Jeffrey A. Sabrowski ,  Anuwat Saetow

    IPC分类号： G11C11/406 ,  G11C11/4076

    CPC分类号： G11C11/406 ,  G11C7/24 ,  G11C11/403 ,  G11C11/40603 ,  G11C11/4076

    摘要： A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

    摘要翻译： 一种用于在预定刷新之前刷新存储器设备的行的方法和装置。 存储器阵列可以包括多个存储器单元。 存储器阵列可以被配置为在第一刷新时间间隔被刷新。 存储器件还可以包括中间刷新电路。 中间刷新电路可以被配置为响应于检测到触发事件来检测触发事件并请求针对存储器阵列的刷新。

    IMPLEMENTING ENHANCED RELIABILITY OF SYSTEMS UTILIZING DUAL PORT DRAM
    39.
    发明申请
    IMPLEMENTING ENHANCED RELIABILITY OF SYSTEMS UTILIZING DUAL PORT DRAM 有权
    实现双端口DRAM系统的增强可靠性

    公开(公告)号：US20150278005A1

    公开(公告)日：2015-10-01

    申请号：US14312327

    申请日：2014-06-23

    申请人： International Business Machines Corporation

    发明人： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

    IPC分类号： G06F11/07

    CPC分类号： G06F12/0238 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/108 ,  G06F2212/251

    摘要： A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于利用双端口动态随机存取存储器（DRAM）配置来实现存储器子系统的增强的可靠性。 DRAM配置包括第一缓冲器和第二缓冲器，每个缓冲器包括有效性计数器。 接收缓冲器的有效性计数器随着来自传送缓冲器的每个相应数据行通过纠错码（ECC），可靠性，可用性和可服务性（RAS）逻辑被验证并递送到接收缓冲器而增加，而有效性计数器 传送缓冲区递减。 基于有效性计数器的相应计数值，从第一缓冲器或第二缓冲器读取或写入数据。

    SELF MONITORING AND SELF REPAIRING ECC
    40.
    发明申请
    SELF MONITORING AND SELF REPAIRING ECC 有权
    自我监测和自我修复ECC

    公开(公告)号：US20150178147A1

    公开(公告)日：2015-06-25

    申请号：US14623706

    申请日：2015-02-17

    申请人： International Business Machines Corporation

    发明人： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

    IPC分类号： G06F11/10 ,  H03M13/29

    CPC分类号： G06F11/10 ,  G06F11/1048 ,  G06F11/2017 ,  G06F11/28 ,  H03M13/29

    摘要： Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

    摘要翻译： 本发明的示例性实施例公开了一种用于监视第一纠错码（ECC）设备的方法和系统，用于如果第一ECC设备开始失败或失败，则用第二ECC设备故障并替换第一ECC设备。 在一个步骤中，如果超过指定数量的可校正错误或者发生不可校正的错误，则示例性实施例对ECC设备执行环回测试。 在另一步骤中，示例性实施例用通过环回测试的ECC设备替代了对环回测试失败的ECC设备。