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公开(公告)号：US20150130510A1
公开(公告)日：2015-05-14
申请号：US14074926
申请日：2013-11-08
Applicant: International Business Machines Corporation
Inventor： Igor Arsovski , Travis R. Hebig
IPC: H03K19/00 , H03K19/0944
CPC classification number: H03K19/0013 , H03K5/135 , H03K19/0944 , H03K19/0963
Abstract: An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch.
Abstract translation: 输出驱动器电路可以包括导电介质，输出逻辑反相器，其具有适于将第一正电源电压耦合到导电介质的第一开关和适于将接地电源电压耦合到导电介质的第二开关。 第一偏置网络包括耦合到导电介质的第一输入端，接收时钟信号的第二输入端和适于将第二正电源电压耦合到第一和第二开关的每个输入端的第一输出端。 基于将导电介质耦合到接地电源电压并且接收的时钟信号产生逻辑低的第二开关，偏置网络通过将第二正电源电压耦合到第一开关的相应输入端而产生泄漏来反向偏置第一开关，导致泄漏 当前减少了第一个开关。
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公开(公告)号：US20140201579A1
公开(公告)日：2014-07-17
申请号：US13742733
申请日：2013-01-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Igor Arsovski , Sebastian T. Ventrone
Abstract: Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays. The finite state machines are sensitive to a predetermined sequence of addresses sent to the memory array or the time between a series of memory array errors detected by an error detection circuit. Upon detection of the pre-set addresses or errors the finite state machines either (i) enable or disable specific circuit functions or (ii) disrupt the operation of the integrated circuit.
Abstract translation: 破坏集成电路功能的方法和电路。 这些电路包括连接到存储器阵列的有限状态机。 有限状态机对发送到存储器阵列的预定的地址序列或由错误检测电路检测的一系列存储器阵列错误之间的时间敏感。 在检测到预设地址或错误时，有限状态机可以（i）启用或禁用特定的电路功能，或（ii）中断集成电路的操作。
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公开(公告)号：US10991428B2
公开(公告)日：2021-04-27
申请号：US16743695
申请日：2020-01-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Igor Arsovski , Suparna Bhattacharya , Arvind Kumar
Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.
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Patent Agency Ranking
公开(公告)号：US09501607B1
公开(公告)日：2016-11-22
申请号：US14734411
申请日：2015-06-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Igor Arsovski , Mark W. Kuemerle , Qing Li
CPC classification number: G06F17/5081 , G06F17/5027 , G06F17/5031 , G06F17/5045 , G06F17/5077 , G06F2217/06 , G06F2217/66 , G06F2217/84
Abstract: A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.
Abstract translation: 用于知识产权（IP）核心的生成复合视图的计算设备可以获得其中使用IP核的多个专用集成电路（ASIC）设计的约束; 并基于多个ASIC设计的约束来确定IP核的复合约束。 复合约束可以在多个ASIC设计的所有约束内。 可以基于复合约束来识别更新特定IP核的自由。
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公开(公告)号：US20150194194A1
公开(公告)日：2015-07-09
申请号：US14146793
申请日：2014-01-03
Applicant: International Business Machines Corporation
Inventor： Igor Arsovski , Travis R. Hebig
CPC classification number: G11C7/08 , G11C7/067 , G11C7/12 , G11C15/04 , G11C2207/002
Abstract: Disclosed are single-ended sensing circuits. Each of the sensing circuits comprises at least a sense amplifier connected to a sense node, an isolation field effect transistor (FET) connected in series between the sense node and a signal line node, and a pre-charged device connected to the sense node. In order to achieve a relatively fast pre-charge of both the sense and signal line nodes and to also achieve a relatively fast and accurate sense of the sense node, the single-ended circuits further incorporate a variable reference voltage generator connected to the gate of the isolation FET for selectively applying different reference voltages to the gate during pre-charging and sensing operations, respectively, and/or a second pre-charge device connected to the signal line node for facilitating pre-charging of that signal line node.
Abstract translation: 公开了单端感测电路。 每个感测电路至少包括连接到感测节点的读出放大器，串联连接在感测节点和信号线节点之间的隔离场效应晶体管（FET）以及连接到感测节点的预充电器件。 为了实现感测和信号线路节点的相对较快的预充电并且还实现感测节点的相对快速和准确的感测，单端电路还包括连接到门极的可变参考电压发生器 隔离FET分别用于在预充电和感测操作期间选择性地将不同的参考电压施加到栅极，和/或连接到信号线节点的第二预充电器件用于促进该信号线节点的预充电。
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公开(公告)号：US20150025857A1
公开(公告)日：2015-01-22
申请号：US13947155
申请日：2013-07-22
Applicant: International Business Machines Corporation
Inventor： Igor Arsovski , Robert M. Houle , Mark W. Kuemerle
IPC: G06F17/50
CPC classification number: G06F17/5045 , G06F17/5022 , G06F2217/10 , G06F2217/78
Abstract: A method for predicting the power consumption of a semiconductor chip is provided. A plurality of statistical distributions characterizing a plurality of power contributing parameters for a plurality of power consuming units included in the semiconductor chip is received. A statistical distribution characterizing the power consumption is determined based on the received plurality of statistical distributions and based on the correlation between the plurality of power contributing parameters.
Abstract translation: 提供了一种用于预测半导体芯片的功耗的方法。 接收表示包括在半导体芯片中的多个功率消耗单元的多个功率贡献参数的多个统计分布。 基于接收到的多个统计分布并且基于多个功率贡献参数之间的相关性来确定表征功耗的统计分布。
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37.发明授权公开(公告)号：US08929116B2
公开(公告)日：2015-01-06
申请号：US13733973
申请日：2013-01-04
Applicant: International Business Machines Corporation
Inventor： Igor Arsovski , Michael T. Fragano , Travis R. Hebig
Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.
Abstract translation: 低泄漏CAM和低泄漏CAM的搜索方法。 该方法包括在主搜索CAM单元被供电到较低电压电平的同时，在少量的预搜索位与所有供电至正常电压电平的预搜索CAM单元之间执行预搜索和比较。 只有在预搜索位上检测到匹配，主激活的CAM单元才能上电到正常的电压电平，激活主搜索位的搜索。 主读取CAM单元在读取和写入操作期间被供电到正常的电压电平。
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38.发明申请公开(公告)号：US20140192579A1
公开(公告)日：2014-07-10
申请号：US13733973
申请日：2013-01-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Igor Arsovski , Michael T. Fragano , Travis R. Hebig
Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.
Abstract translation: 低泄漏CAM和低泄漏CAM的搜索方法。 该方法包括在主搜索CAM单元被供电到较低电压电平的同时，在少量的预搜索位与所有供电至正常电压电平的预搜索CAM单元之间执行预搜索和比较。 只有在预搜索位上检测到匹配，主激活的CAM单元才能上电到正常的电压电平，激活主搜索位的搜索。 主读取CAM单元在读取和写入操作期间被供电到正常的电压电平。
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