公开(公告)号：US20140353825A1

公开(公告)日：2014-12-04

申请号：US13904744

申请日：2013-05-29

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/285 ,  H01L23/532

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/20

Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.

公开(公告)号：US08901655B2

公开(公告)日：2014-12-02

申请号：US13969820

申请日：2013-08-19

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L27/13 ,  H01L29/86 ,  B82Y99/00

CPC classification number: H01L29/66545 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/888 ,  Y10S977/938

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中图案化至少一个第一/第二组纳米线和焊盘。 围绕用作晶体管器件的沟道区的第一组纳米线的每一个的一部分选择性地形成共形栅介质层。 第一金属栅极堆叠形成在共形栅极介电层上，围绕作为晶体管器件的沟道区域的第一组纳米线的每一个的栅极全部构型。 形成第二金属栅极叠层，围绕作为二极管器件的栅极全部配置的沟道区的第二组纳米线的每一个的一部分。

公开(公告)号：US08901616B2

公开(公告)日：2014-12-02

申请号：US14027398

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L31/113 ,  H01L21/336 ,  H01L21/31 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底上形成高k栅介质层，其中含有界面层的氧化物可以存在于高k栅介质层和半导体衬底之间。 清除金属堆叠可以形成在高k栅极电介质层上。 可以将清除金属堆叠的清除金属堆叠中的退火工艺应用于其中，其中清除金属堆叠从含氧化物的界面层去除氧化物材料，其中通过除去氧化物材料使含有氧化物的界面层变薄。 栅极导体层形成在高k栅介质层上。 然后对栅极导体层和高k栅极电介质层进行构图以提供栅极结构。 然后在栅极结构的相对侧上形成源极区域和漏极区域。

公开(公告)号：US08900952B2

公开(公告)日：2014-12-02

申请号：US13793290

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/336 ,  H01L21/26 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底上形成高k栅介质层，其中含有界面层的氧化物可以存在于高k栅介质层和半导体衬底之间。 清除金属堆叠可以形成在高k栅极电介质层上。 可以将清除金属堆叠的清除金属堆叠中的退火工艺应用于其中，其中清除金属堆叠从含氧化物的界面层去除氧化物材料，其中通过除去氧化物材料使含有氧化物的界面层变薄。 栅极导体层形成在高k栅介质层上。 然后对栅极导体层和高k栅极电介质层进行构图以提供栅极结构。 然后在栅极结构的相对侧上形成源极区域和漏极区域。

公开(公告)号：US20140332890A1

公开(公告)日：2014-11-13

申请号：US14023868

申请日：2013-09-11

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

Abstract translation: 在绝缘体层上形成至少一个半导体鳍片。 绝缘体层的一部分从至少一个半导体鳍片的下方蚀刻。 选择绝缘体的蚀刻部分的量使得金属栅极电极层填充绝缘体层的凹陷表面和至少一个半导体鳍片的底表面之间的整个间隙。 金属栅极电极层和半导体栅极电极层之间的界面在该至少一个半导体鳍片上连续地延伸，并且不在至少一个半导体鳍片的任何一个之下。 在栅电极的图形化期间，由于半导体栅极电极层不存在于至少一个半导体鳍片之下，所以能够促进半导体栅极电极层中的半导体材料的去除。

公开(公告)号：US08859410B2

公开(公告)日：2014-10-14

申请号：US13828846

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/336 ,  H01L29/423

CPC classification number: H01L29/511 ,  H01L21/28044 ,  H01L21/2807 ,  H01L29/42364 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/78

Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

Abstract translation: 一种形成半导体器件的栅极结构的方法，包括在半导体衬底上形成非化学计量的高k栅极电介质层，其中含有界面层的氧化物可以存在于非化学计量的高k栅极电介质层和 半导体衬底。 可以在非化学计量的高k栅极电介质层上形成至少一个栅极导体层。 所述至少一个栅极导体层包括硼半导体合金层。 应用退火工艺，其中在退火工艺期间，非化学计量的高k栅极电介质层从含氧化物界面层去除氧化物材料。 通过在退火过程中除去氧化物材料，使含氧化物的界面层变薄。

公开(公告)号：US20140264639A1

公开(公告)日：2014-09-18

申请号：US14030520

申请日：2013-09-18

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/511 ,  H01L21/28044 ,  H01L21/2807 ,  H01L29/42364 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/78

Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

公开(公告)号：US20140252493A1

公开(公告)日：2014-09-11

申请号：US14027398

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.

公开(公告)号：US20140217508A1

公开(公告)日：2014-08-07

申请号：US13967888

申请日：2013-08-15

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/861

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

公开(公告)号：US20140217364A1

公开(公告)日：2014-08-07

申请号：US13971974

申请日：2013-08-21

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleights

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66136 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/938

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract translation: 一方面，一种制造电子设备的方法包括以下步骤。 在SOI晶片上的堆叠中形成交替的器件和牺牲层系列。 将纳米线棒蚀刻到器件/牺牲层中，使得堆叠的第一部分中的每个器件层和堆叠的第二部分中的每个器件层具有源极区，漏极区和多个纳米线 通道连接源极区域和漏极区域。 从纳米线条之间移除牺牲层。 选择性地形成围绕堆叠的第一部分中的纳米线通道的共形栅极介电层，其用作纳米级FET晶体管的沟道区。 在堆叠的第一和第二部分中围绕纳米线通道形成栅极。