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31.发明申请公开(公告)号：US20220406377A1
公开(公告)日：2022-12-22
申请号：US17304503
申请日：2021-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Fabio Carta , Matthew Joseph BrightSky , Wanki Kim , Maxence Bouvier , SangBum Kim
Abstract: According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to amorphize the phase change material of the PCM cell; responsive to applying the RESET pulse, applying an incubation pulse to the PCM cell; and applying a plurality of partial SET pulses to incrementally increase the conductance of the PCM cell.
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32.发明授权公开(公告)号：US11216595B2
公开(公告)日：2022-01-04
申请号：US16578319
申请日：2019-09-21
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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33.发明授权公开(公告)号：US10997321B2
公开(公告)日：2021-05-04
申请号：US16578321
申请日：2019-09-21
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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34.发明授权公开(公告)号：US10825514B2
公开(公告)日：2020-11-03
申请号：US15958833
申请日：2018-04-20
Applicant: International Business Machines Corporation
Inventor： Wanki Kim , Matthew Joseph BrightSky , Yu Zhu , Yujun Xie
Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.
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公开(公告)号：US10692574B2
公开(公告)日：2020-06-23
申请号：US16290353
申请日：2019-03-01
Applicant: International Business Machines Corporation
Inventor： Wanki Kim , Chung Hon Lam , Yu Zhu , Yujun Xie
Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.
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Patent Agency Ranking
36.发明申请公开(公告)号：US20190325954A1
公开(公告)日：2019-10-24
申请号：US15958833
申请日：2018-04-20
Applicant: International Business Machines Corporation
Inventor： Wanki Kim , Matthew Joseph BrightSky , Yu Zhu , Yujun Xie
Abstract: The embodiments described herein facilitate performing bipolar switching of a confined phase change memory (PCM) with a metallic liner, wherein the phase change memory and the metallic liner are located between a first electrode and a second electrode of a semiconductor structure, wherein a first voltage is applied to the first electrode while the second electrode is grounded, and wherein a second voltage is applied to the second electrode while the first electrode is grounded. The bipolar switching can be performed so as to produce a plurality of resistance states. Thus, this confined PCM can be utilized as a multi-level cell (MLC) memory.
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公开(公告)号：US10319440B1
公开(公告)日：2019-06-11
申请号：US15937176
申请日：2018-03-27
Applicant: International Business Machines Corporation
Inventor： Wanki Kim , Chung Hon Lam , Yu Zhu , Yujun Xie
Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.
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38.发明申请公开(公告)号：US20180181774A1
公开(公告)日：2018-06-28
申请号：US15389078
申请日：2016-12-22
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
IPC: G06F21/72 , G06F21/75 , H01L27/112 , H01L23/00
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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公开(公告)号：US09972660B2
公开(公告)日：2018-05-15
申请号：US15703873
申请日：2017-09-13
Inventor： Hsiang-Lan Lung , Wanki Kim , Matthew J. Brightsky , Chung Hon Lam
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1625 , H01L45/1675
Abstract: A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.
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公开(公告)号：US09793323B1
公开(公告)日：2017-10-17
申请号：US15207022
申请日：2016-07-11
Inventor： Hsiang-Lan Lung , Wanki Kim , Matthew J. Brightsky , Chung Hon Lam
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1625 , H01L45/1675
Abstract: A plurality of memory cells in a cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.
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