公开(公告)号：US11968913B2

公开(公告)日：2024-04-23

申请号：US17876237

申请日：2022-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wanki Kim ,  Fabio Carta ,  Chung H. Lam ,  Robert L. Bruce

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10B63/84 ,  H10N70/023 ,  H10N70/026 ,  H10N70/063 ,  H10N70/231 ,  H10N70/841 ,  H10N70/861 ,  H10N70/882

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

公开(公告)号：US20190148453A1

公开(公告)日：2019-05-16

申请号：US16227019

申请日：2018-12-20

Applicant: International Business Machines Corporation

Inventor： Robert Bruce ,  Fabio Carta ,  Gloria WingYun Fraczak ,  Hiroyuki Miyazoe ,  Kumar R. Virwani

IPC: H01L27/24 ,  H01L45/00

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

公开(公告)号：US20160359013A1

公开(公告)日：2016-12-08

申请号：US15212304

申请日：2016-07-18

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Daniel C. Edelstein ,  Stephen M. Gates ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L29/735 ,  H01L21/311

CPC classification number: H01L29/6625 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32105 ,  H01L21/324 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract translation: 双极结型晶体管包括设置在绝缘材料上的半导体层，半导体层的至少一部分形成基极区域。 所述双极结晶体管还包括横向设置在所述基极区域的第一侧上的晶体管发射极，其中所述晶体管发射极是第一掺杂型并具有第一宽度，并且其中所述第一宽度是光刻特征尺寸。 双极结晶体管还包括横向设置在基极区的第二侧上的晶体管集电极，其中晶体管集电极是第一掺杂型和第一宽度。 双极结晶体管还包括横向设置在晶体管发射极和晶体管集电极之间的基极区上的中心基极接触，其中中心基极接触是第二掺杂型并具有第二宽度，并且其中第二宽度是亚晶体， 光刻特征尺寸。

公开(公告)号：US20160218200A1

公开(公告)日：2016-07-28

申请号：US14602799

申请日：2015-01-22

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Daniel C. Edelstein ,  Stephen M. Gates ,  Bahman Hekmatshoartabari ,  Tak H. Ning

IPC: H01L29/735 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L21/225 ,  H01L23/31 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/08 ,  H01L23/29

CPC classification number: H01L29/6625 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32105 ,  H01L21/324 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

公开(公告)号：US11437571B2

公开(公告)日：2022-09-06

申请号：US16451178

申请日：2019-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wanki Kim ,  Fabio Carta ,  Chung H. Lam ,  Robert L. Bruce

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

公开(公告)号：US20210184113A1

公开(公告)日：2021-06-17

申请号：US16718077

申请日：2019-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ning Li ,  Fabio Carta ,  Devendra K. Sadana ,  Tze-Chiang Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: A cross-point memory semiconductor structure and a method of creating the same are provided. There is a first electrode layer on top of the substrate. A conductive oxide diffusion barrier layer is on top of the first electrode. A polycrystalline silicon diode is on top of the conductive oxide diffusion barrier. A phase change material (PCM) layer is on top of the polycrystalline silicon diode. A second electrode is on top of the PCM layer.

公开(公告)号：US10903270B2

公开(公告)日：2021-01-26

申请号：US16227091

申请日：2018-12-20

Applicant: International Business Machines Corporation

Inventor： Robert Bruce ,  Fabio Carta ,  Gloria WingYun Fraczak ,  Hiroyuki Miyazoe ,  Kumar R. Virwani

IPC: H01L45/00 ,  H01L27/24

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

公开(公告)号：US20200295083A1

公开(公告)日：2020-09-17

申请号：US16355292

申请日：2019-03-15

Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huai-Yu CHENG ,  I-Ting KUO ,  Hsiang-Lan LUNG ,  Robert L. Bruce ,  Fabio Carta

IPC: H01L27/24 ,  H01L45/00

Abstract: A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes. An in situ barrier layer is disposed between the first and second electrodes. The barrier layer comprises a composition including silicon and carbon. The switching device can be used in memory devices, including 3D cross-point memory.

公开(公告)号：US20180205017A1

公开(公告)日：2018-07-19

申请号：US15408392

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Fabio Carta ,  Wanki Kim ,  Chung H. Lam

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：US20240196628A1

公开(公告)日：2024-06-13

申请号：US18080721

申请日：2022-12-13

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Praneet Adusumilli ,  Fabio Carta

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H01L27/2445 ,  H01L45/06 ,  H01L45/16

Abstract: A phase change memory device or a ReRAM device is integrated with a pair of bipolar junction transistors, the pair of bipolar junction transistors being arranged in a Sziklai Darlington transistor configuration. A small unit cell footprint is obtained by pairing a vertical bipolar junction transistor with a lateral bipolar junction transistor, the memory device being electrically connected to the collector of the lateral bipolar junction transistor.