公开(公告)号：US11889773B2

公开(公告)日：2024-01-30

申请号：US18172385

申请日：2023-02-22

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Jin Ping Han ,  Timothy Mathew Philip ,  Matthew Joseph BrightSky ,  Nicole Saulnier

IPC: G11C11/00 ,  H10N70/20 ,  G11C11/54 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  G06N3/065

CPC classification number: H10N70/231 ,  G11C11/54 ,  G11C13/0004 ,  H10B63/24 ,  H10N70/826 ,  H10N70/8413 ,  G06N3/065 ,  G11C2213/72

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

公开(公告)号：US20170222141A1

公开(公告)日：2017-08-03

申请号：US15489368

申请日：2017-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew Joseph BrightSky ,  SangBum Kim ,  Chung Hon Lam ,  Norma Edith Sosa

IPC: H01L45/00

CPC classification number: H01L45/124 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

Abstract: Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

公开(公告)号：US09627612B2

公开(公告)日：2017-04-18

申请号：US14633264

申请日：2015-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew Joseph BrightSky ,  SangBum Kim ,  Chung Hon Lam ,  Norma Edith Sosa Cortes

IPC: H01L45/00

CPC classification number: H01L45/124 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

Abstract: Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

公开(公告)号：US11723293B2

公开(公告)日：2023-08-08

申请号：US17213283

申请日：2021-03-26

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Cheng-Wei Cheng ,  Matthew Joseph BrightSky

IPC: H01L45/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8413 ,  H10N70/011 ,  H10N70/231 ,  H10N70/826

Abstract: Aspects of the present invention provide a semiconductor structure for a phase change memory device that includes a heater element on a bottom electrode that is surrounded by a dielectric material. The phase change memory device includes a metal nitride liner over the heater element, where the metal liner is oxide-free with a desired electrical resistance. The phase change memory device includes a phase change material is over the heater element and the dielectric material and a top electrode is over the phase change material.

公开(公告)号：US11562931B2

公开(公告)日：2023-01-24

申请号：US17350014

申请日：2021-06-17

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew Joseph BrightSky

IPC: H01L21/8234 ,  H01L27/24 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

公开(公告)号：US20220406843A1

公开(公告)日：2022-12-22

申请号：US17350014

申请日：2021-06-17

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew Joseph BrightSky

IPC: H01L27/24 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

公开(公告)号：US20220165949A1

公开(公告)日：2022-05-26

申请号：US17104360

申请日：2020-11-25

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Iqbal Rashid Saraf ,  Nicole Saulnier ,  Matthew Joseph BrightSky ,  ROBERT L. BRUCE

IPC: H01L45/00 ,  H01L27/24

Abstract: A mushroom type phase change memory (PCM) cell includes a projection liner located between a PCM volume and a bottom electrode. The projection liner has been retained from a layer previously utilized as an etch stop layer during the fabrication of PCM cell and/or the fabrication of the higher level IC device. The projection liner may extend beyond the PCM sidewall(s) or side boundary. This section of the projection liner may be located or buried under a dielectric or an encapsulation spacer and may increase thickness uniformity of the projection liner below the PCM volume.

公开(公告)号：US20210375360A1

公开(公告)日：2021-12-02

申请号：US17404157

申请日：2021-08-17

Applicant: International Business Machines Corporation ,  Macronix International Co., Ltd.

Inventor： Nanbo Gong ,  Wei-Chih Chien ,  Matthew Joseph BrightSky ,  Christopher P. Miller ,  Hsiang-Lan Lung

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

公开(公告)号：US20250017023A1

公开(公告)日：2025-01-09

申请号：US18217648

申请日：2023-07-03

Applicant: International Business Machines Corporation

Inventor： Ghazi Sarwat Syed ,  Timothy Mathew Philip ,  Vara Sudananda Prasad Jonnalagadda ,  Abu Sebastian ,  Matthew Joseph BrightSky

IPC: H10B63/10 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: Semiconductor devices and methods for forming the semiconductor devices are described. A semiconductor device can include a first electrode, a storage node, a second electrode and a film layer. The storage node can include phase change material deposited on top of the first electrode. The film layer can be deposited on top of the storage node and connected in a closed circuit. A voltage difference among the first electrode, the second electrode and the film layer can dictate a threshold voltage that triggers a phase change of the phase change material. An amorphous volume in the storage node can be dependent on a structural arrangement of the first electrode, the second electrode and the film layer with respect to the storage node.

公开(公告)号：US11647683B2

公开(公告)日：2023-05-09

申请号：US16576834

申请日：2019-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Matthew Joseph BrightSky ,  Praneet Adusumilli

IPC: H01L29/66

CPC classification number: H10N70/828 ,  H10N70/011 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413

Abstract: A method may include forming a bottom electrode in an interlayer dielectric, depositing a liner on top of the bottom electrode, depositing a phase change material layer on top of the liner, wherein a top surface of the liner is in direct contact with a bottom surface of the phase change material layer, and depositing a barrier on top of the phase change material layer, wherein a top surface of the phase change material layer is in direct contact with a bottom surface of the barrier. The barrier may be made of doped phase change material. The forming of the bottom electrode may further include forming a via in the interlayer dielectric, depositing an outer layer along a bottom and a sidewall of the via, depositing a middle layer on top of the outer layer, and depositing an inner layer on top of the middle layer.