公开(公告)号：US10971546B2

公开(公告)日：2021-04-06

申请号：US16542929

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Fabio Carta ,  Matthew J. BrightSky ,  Bahman Hekmatshoartabari ,  Asit Ray ,  Wanki Kim

IPC: H01L27/24 ,  H01L21/3213 ,  H01L45/00 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

公开(公告)号：US20200019731A1

公开(公告)日：2020-01-16

申请号：US16578319

申请日：2019-09-21

Applicant: International Business Machines Corporation

Inventor： Richard H. Boivie ,  Eduard A. Cartier ,  Daniel J. Friedman ,  Kohji Hosokawa ,  Charanjit Jutla ,  Wanki Kim ,  Chandrasekara Kothandaraman ,  Chung Lam ,  Frank R. Libsch ,  Seiji Munetoh ,  Ramachandran Muralidhar ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Robert L. Wisnieff

IPC: G06F21/72 ,  G11C16/00 ,  G06F21/75

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

公开(公告)号：US20240196766A1

公开(公告)日：2024-06-13

申请号：US18063189

申请日：2022-12-08

Applicant: International Business Machines Corporation

Inventor： Matthew Joseph BrightSky ,  Cheng-Wei Cheng ,  Guy M. Cohen ,  Robert L. Bruce ,  Asit Ray ,  Wanki Kim

IPC: H01L47/00

CPC classification number: H01L45/1246 ,  H01L45/06 ,  H01L45/144

Abstract: An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.

公开(公告)号：US11968913B2

公开(公告)日：2024-04-23

申请号：US17876237

申请日：2022-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wanki Kim ,  Fabio Carta ,  Chung H. Lam ,  Robert L. Bruce

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10B63/84 ,  H10N70/023 ,  H10N70/026 ,  H10N70/063 ,  H10N70/231 ,  H10N70/841 ,  H10N70/861 ,  H10N70/882

Abstract: A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

公开(公告)号：US11164628B2

公开(公告)日：2021-11-02

申请号：US16797626

申请日：2020-02-21

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Wanki Kim ,  Stephen W. Bedell ,  Devendra K. Sadana

IPC: G11C11/00 ,  G11C13/00 ,  G06N3/063

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

公开(公告)号：US20210288250A1

公开(公告)日：2021-09-16

申请号：US16817912

申请日：2020-03-13

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Wanki Kim ,  Devendra K. Sadana

IPC: H01L45/00

Abstract: A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.

公开(公告)号：US20210264978A1

公开(公告)日：2021-08-26

申请号：US16797626

申请日：2020-02-21

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Wanki Kim ,  Stephen W. Bedell ,  Devendra K. Sadana

IPC: G11C13/00 ,  G06N3/063

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

公开(公告)号：US10832773B1

公开(公告)日：2020-11-10

申请号：US16458806

申请日：2019-07-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Seyoung Kim ,  Tayfun Gokmen ,  Nanbo Gong ,  Wanki Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06 ,  G11C7/10

Abstract: A system includes an analog memory architecture for performing differential reading. The analog memory architecture includes a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, and a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires. The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.

公开(公告)号：US20190311082A1

公开(公告)日：2019-10-10

申请号：US16433675

申请日：2019-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Li-Wen Hung ,  Wanki Kim ,  John U. Knickerbocker ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: G06F17/50 ,  H01L25/07 ,  G06F15/78 ,  H01L25/11 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

公开(公告)号：US20190304541A1

公开(公告)日：2019-10-03

申请号：US16290353

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Chung Hon Lam ,  Yu Zhu ,  Yujun Xie

IPC: G11C13/00 ,  H01L45/00 ,  H01L21/66

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.