公开(公告)号：US20210117347A1

公开(公告)日：2021-04-22

申请号：US17134089

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Barnes Cooper ,  Abdul R. Ismail

IPC: G06F13/16 ,  G06F1/3234 ,  G06T1/20

Abstract: Techniques for controlling input/output (I/O) power usage are disclosed. In the illustrative embodiment, a power policy engine of a compute device monitors power usage, I/O data transfer rates, and temperature and determines when there should be a change in an I/O power setting. The I/O data transfer requires that the data be handled properly, causing the compute device to expend power on the I/O data transfer. The power policy engine may instruct a device driver, such as a driver of an I/O device, to change a data transfer rate of the I/O device, reducing the power the compute device spends handling I/O.

公开(公告)号：US20200264925A1

公开(公告)日：2020-08-20

申请号：US16866371

申请日：2020-05-04

Applicant: INTEL CORPORATION

Inventor： Barnes Cooper

IPC: G06F9/48

Abstract: A power delivery system of a computing system that is on alternating current (AC) power limits software administrative tasks to a system-controlled and tunable broadcast window. This window limitation allows a computing system to enter and stay in low-power states without variable disturbances from administrative functions that can be relegated to the window. For example, maintenance is restricted until the computing system broadcasts a notification. Legacy software and devices that do not understand these notifications can be told the AC power is not present nominally, and then be notified of AC power presence during maintenance intervals.

公开(公告)号：US10317974B2

公开(公告)日：2019-06-11

申请号：US15094367

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Barnes Cooper

IPC: G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/3287

Abstract: In one example an electronic device comprises a power supply comprising an operating power rail and a standby power rail, a processing platform capable to switch between an operating power state and at least one low power state, a switch to selectively couple a power input of the processing platform to one of the operating power rail or the standby power output rail and logic, at least partially including hardware logic, to activate the switch based at least in part on the operating state of the processing platform. Other examples may be described.

公开(公告)号：US20170371738A1

公开(公告)日：2017-12-28

申请号：US15191283

申请日：2016-06-23

Applicant: INTEL CORPORATION

Inventor： Barnes Cooper

IPC: G06F11/07

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: A power delivery system of a computing system that is on alternating current (AC) power limits software administrative tasks to a system-controlled and tunable broadcast window. This window limitation allows a computing system to enter and stay in low-power states without variable disturbances from administrative functions that can be relegated to the window. For example, maintenance is restricted until the computing system broadcasts a notification. Legacy software and devices that do not understand these notifications can be told the AC power is not present nominally, and then be notified of AC power presence during maintenance intervals.

公开(公告)号：US20170371402A1

公开(公告)日：2017-12-28

申请号：US15191123

申请日：2016-06-23

Applicant: INTEL CORPORATION

Inventor： Barnes Cooper ,  Neil W. Songer

IPC: G06F1/32 ,  G06F1/26 ,  G05B15/02

Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.

公开(公告)号：US20170177068A1

公开(公告)日：2017-06-22

申请号：US14972461

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Barnes Cooper ,  Vidoot Ponnala Rathnakar

IPC: G06F1/32 ,  G06F1/26

Abstract: A power delivery system of a computing system can switch the computing platform from a set of main rails to a standby rail in a low-power state. For example, using a power optimizer framework, a platform controller hardware (PCH) and/or platform management controller (PCU) can transition an idle computing system to a low-power state using a standby rail with the main rails off. The PCU can instruct a processor in a C10 state to switch from main power rails to a standby rail. Once confirmed that the processor is in the C10 state, the PCU can turn off a processor voltage regulator and assert a platform sleep signal. After confirming the platform has entered the sleep state in which the platform has moved to the standby rails, the PCH or PCU can request a power supply to turn off the main rails but leave the standby rail active.

公开(公告)号：US09541983B2

公开(公告)日：2017-01-10

申请号：US14919780

申请日：2015-10-22

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R Wilcox ,  Michael N Derr ,  Neil W Songer ,  Craig S Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。

公开(公告)号：US09494998B2

公开(公告)日：2016-11-15

申请号：US14109388

申请日：2013-12-17

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Faraz A. Siddiqi ,  Michael Calyer ,  Andrew D. Henroid ,  Ruchika Singh

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为 重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。 描述和要求保护其他实施例。

公开(公告)号：US09158357B2

公开(公告)日：2015-10-13

申请号：US13730625

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Linda Weyhing ,  Rajeev Nalawadi ,  Barnes Cooper ,  Suraj Varma ,  Nevo Idan ,  David Poisner

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  Y02D10/171

Abstract: In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.

Abstract translation: 在本文描述的至少一个实施例中，提供了一种装置，其可以包括用于如果软件等待时间容差寄存器模式是活动的，则用于在软件等待时间寄存器中传送连接到平台的设备的等待时间容限值的装置。 该装置还可以包括用于在主机控制器处于活动状态时从硬件等待时间寄存器传送等待时间容差值的装置。 延迟容限值可以发送到电源管理控制器。 更具体的示例可以包括用于在软件延迟容限寄存器模式不活动且主机控制器不活动的情况下从软件延迟寄存器传送延迟容限值的装置。 该装置还可以包括用于使用BIOS /平台驱动器在设备的软件延迟寄存器中映射资源空间的装置。 可以使用高级配置和电源接口设备描述来实现映射。

公开(公告)号：US12210604B2

公开(公告)日：2025-01-28

申请号：US18322270

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Aleksander Magi ,  Barnes Cooper ,  Arvind Kumar ,  Julio Zamora Esquivel ,  Vivek Paranjape ,  William Lewis ,  Marko Bartscherer ,  Giuseppe Raffa

IPC: G06F21/00 ,  G06F21/32 ,  G06V40/16 ,  G10L17/00 ,  G10L17/06

Abstract: Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.