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    Stepped interposer for stacked chip package
    36.
    发明授权
    Stepped interposer for stacked chip package 有权

    公开(公告)号：US11527479B2

    公开(公告)日：2022-12-13

    申请号：US17089744

    申请日：2020-11-05

    Applicant: Intel Corporation

    Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

    IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L23/64 ,  H01L21/56 ,  H01L23/50

    Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

    Interposer for hybrid interconnect geometry
    37.
    发明授权
    Interposer for hybrid interconnect geometry 有权

    公开(公告)号：US11508650B2

    公开(公告)日：2022-11-22

    申请号：US17023042

    申请日：2020-09-16

    Applicant: Intel Corporation

    Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/64

    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.

    Multi-faceted integrated-circuit dice and packages
    38.
    发明授权
    Multi-faceted integrated-circuit dice and packages 有权

    公开(公告)号：US11289427B2

    公开(公告)日：2022-03-29

    申请号：US16818558

    申请日：2020-03-13

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

    IPC: H01L21/00 ,  H01L23/538 ,  H01L23/48

    Abstract: A faceted integrated-circuit die includes a concave facet with an increased interconnect breakout area available to an adjacent device such as a rectangular IC die that is nested within the form factor of the concave facet. The concave facet form factor includes a ledge facet and a main-die facet. Multiple nested faceted IC dice are disclosed for increasing interconnect breakout areas and package miniaturization. A faceted silicon interposer has a concave facet that also provides an increased interconnect breakout area and package miniaturization.

    Integrated bridge for die-to-die interconnects
    39.
    发明授权
    Integrated bridge for die-to-die interconnects 有权

    公开(公告)号：US11282780B2

    公开(公告)日：2022-03-22

    申请号：US17025115

    申请日：2020-09-18

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/498 ,  H01G4/12 ,  H01L49/02

    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

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