公开(公告)号：US09875185B2

公开(公告)日：2018-01-23

申请号：US14327109

申请日：2014-07-09

申请人： Intel Corporation

发明人： Chunhui Zhang ,  George Z. Chrysos ,  Edward T. Grochowski ,  Ramacharan Sundararaman ,  Chung-Lun Chan ,  Federico Ardanaz

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0842 ,  G06F12/0817 ,  G06F12/0831 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815

CPC分类号： G06F12/0842 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

摘要： Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

公开(公告)号：US09785436B2

公开(公告)日：2017-10-10

申请号：US13631071

申请日：2012-09-28

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/35 ,  G06F9/345 ,  G06F9/355

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/355

摘要： An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

公开(公告)号：US09477467B2

公开(公告)日：2016-10-25

申请号：US13854089

申请日：2013-03-30

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Seyed Yahya Sotoudeh ,  Buford M. Guy

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3016

摘要： A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.

摘要翻译： 一种方法包括：接收指示第一较窄的源打包数据操作数和较窄的目的地操作数的打包数据指令。 指令被映射到掩码的打包数据操作，指示比第一较窄源操作数宽的第一较宽的源打包数据操作数，并且包括第一较窄的源操作数，并且指示较宽的目的地操作数，并且包括较窄的目的地操作数。 生成打包数据操作掩码，其包括用于通过掩蔽的打包数据操作存储的打包数据结果的每个对应结果数据元素的掩码元素。 对应于由打包数据指令不存储的掩蔽操作存储的结果数据元素的所有掩码元素都将被遮蔽。 使用打包数据操作掩码执行屏蔽操作。 打包数据结果存储在更宽的目标操作数中。

公开(公告)号：US09442721B2

公开(公告)日：2016-09-13

申请号：US13722481

申请日：2012-12-20

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Colins ,  James P. Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/54 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

公开(公告)号：US11698787B2

公开(公告)日：2023-07-11

申请号：US17362854

申请日：2021-06-29

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Asit K. Mishra ,  Robert Valentine ,  Mark J. Charney ,  Simon C. Steely, Jr.

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3861 ,  G06F9/3865

摘要： A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

公开(公告)号：US11416281B2

公开(公告)日：2022-08-16

申请号：US16474978

申请日：2016-12-31

申请人： Intel Corporation

发明人： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38

摘要： Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220237123A1

公开(公告)日：2022-07-28

申请号：US17712632

申请日：2022-04-04

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David B. Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/30

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10579378B2

公开(公告)日：2020-03-03

申请号：US14228016

申请日：2014-03-27

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Victor W. Lee ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC分类号： G06F9/30

摘要： An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

申请人： Intel Corporation

发明人： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC分类号： G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10261904B2

公开(公告)日：2019-04-16

申请号：US15835384

申请日：2017-12-07

申请人： Intel Corporation

发明人： Chunhui Zhang ,  George Z. Chrysos ,  Edward T. Grochowski ,  Ramacharan Sundararaman ,  Chung-Lun Chan ,  Federico Ardanaz

IPC分类号： G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842

摘要： Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.