公开(公告)号：US11782866B2

公开(公告)日：2023-10-10

申请号：US17674030

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4234 ,  G06F13/14 ,  G06F13/38

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

公开(公告)号：US11726927B2

公开(公告)日：2023-08-15

申请号：US17827458

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/42

CPC classification number: G06F13/161 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1063 ,  G06F13/1663 ,  G06F13/4282 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2213/0026

Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

公开(公告)号：US20230035420A1

公开(公告)日：2023-02-02

申请号：US17955353

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US11216396B2

公开(公告)日：2022-01-04

申请号：US15280730

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Raj K. Ramanujan ,  Filip Schmole ,  David M. Lee ,  Ishwar Agarwal ,  David J. Harriman

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/12

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

公开(公告)号：US11036650B2

公开(公告)日：2021-06-15

申请号：US16575478

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Ishwar Agarwal

IPC: G06F12/1081 ,  G06F9/50 ,  G06F13/16 ,  G06F12/0871 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0862

Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.

公开(公告)号：US10970238B2

公开(公告)日：2021-04-06

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20200050570A1

公开(公告)日：2020-02-13

申请号：US16659660

申请日：2019-10-22

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Nitish Paliwal

IPC: G06F13/40 ,  G06F13/20

Abstract: In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.

公开(公告)号：US20200004703A1

公开(公告)日：2020-01-02

申请号：US16566865

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  David J. Harriman ,  Sean O. Stalley ,  Rupin H. Vakharwala ,  Ishwar Agarwal ,  Pratik M. Marolia ,  Stephen R. Van Doren

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

公开(公告)号：US20190278721A1

公开(公告)日：2019-09-12

申请号：US16424875

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Theodros Yigzaw

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0831

Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.

公开(公告)号：US20180189104A1

公开(公告)日：2018-07-05

申请号：US15396529

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Rajesh Sankaran ,  Stephen Van Doren

IPC: G06F9/50 ,  G06F9/455

Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.