公开(公告)号：US20220113756A1

公开(公告)日：2022-04-14

申请号：US17559411

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Mahesh K. Kumashikar

IPC: G06F1/06

Abstract: Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.

公开(公告)号：US11101804B2

公开(公告)日：2021-08-24

申请号：US16711330

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Scott Jeremy Weber ,  Aravind Raghavendra Dasu ,  Mahesh A. Iyer ,  Patrick Koeberl

IPC: H03K19/17756 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

公开(公告)号：US20210216692A1

公开(公告)日：2021-07-15

申请号：US17213021

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Scott Whitty ,  Mahesh A. Iyer

IPC: G06F30/337 ,  G06F30/392

Abstract: Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

公开(公告)号：US10965536B2

公开(公告)日：2021-03-30

申请号：US16370934

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Kermin E. ChoFleming, Jr. ,  Jesmin Jahan Tithi ,  Suresh Srinivasan ,  Mahesh A. Iyer

IPC: H04L12/24 ,  H04L12/26 ,  H04L12/861

Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.

公开(公告)号：US10372850B2

公开(公告)日：2019-08-06

申请号：US15354809

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer

IPC: G06F17/50 ,  G06F1/24

Abstract: Circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the modified circuit design after the register moves. The adjustment value may be bound by a user-specified maximum value. This retiming operation may also be verified by performing rewind verification. The rewind verification involves retiming the retimed circuit back to the original circuit, while respecting the counter values. If verification succeeds, the circuit design may be reset using a smaller adjustment value. If verification fails, a correct counter value may be suggested for each clock domain.

公开(公告)号：US20190095571A1

公开(公告)日：2019-03-28

申请号：US15718685

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ning Cheng ,  Xiangyong Wang ,  Mahesh A. Iyer

IPC: G06F17/50

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

公开(公告)号：US20180218104A1

公开(公告)日：2018-08-02

申请号：US15422971

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Mahesh A. Iyer

IPC: G06F17/50 ,  G06F13/42

CPC classification number: G06F17/5054 ,  G06F13/42 ,  G06F17/5072

Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.

公开(公告)号：US20180101624A1

公开(公告)日：2018-04-12

申请号：US15391511

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Shounak Dhar ,  Mahesh A. Iyer ,  Love Singhal ,  Nikolay Rubanov ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/84

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed.

公开(公告)号：US20180018416A1

公开(公告)日：2018-01-18

申请号：US15718375

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer ,  Vasudeva M. Kamath

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5045 ,  G06F17/5054 ,  G06F17/5081

Abstract: A method for performing rewind functional verification includes identifying state variables that model the number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

公开(公告)号：US12003238B2

公开(公告)日：2024-06-04

申请号：US17407700

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Scott Jeremy Weber ,  Aravind Raghavendra Dasu ,  Mahesh A. Iyer ,  Patrick Koeberl

IPC: H03K19/177 ,  H01L25/00 ,  H01L25/065 ,  H03K19/17756

CPC classification number: H03K19/17756 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.