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公开(公告)号：US09225521B2
公开(公告)日：2015-12-29
申请号：US14507427
申请日：2014-10-06
Applicant: Intel Corporation
Inventor： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
CPC classification number: H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
Abstract translation: 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。
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公开(公告)号：US20240429901A1
公开(公告)日：2024-12-26
申请号：US18340679
申请日：2023-06-23
Applicant: Intel Corporation
Inventor： Steven K. Hsu , Amit Agarwal , Abhishek Anil Sharma , Ram K. Krishnamurthy
IPC: H03K3/037 , H03K17/687
Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.
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公开(公告)号：US20230376274A1
公开(公告)日：2023-11-23
申请号：US18362529
申请日：2023-07-31
Applicant: Intel Corporation
Inventor： Mark Anders , Arnab Raha , Amit Agarwal , Steven Hsu , Deepak Abraham Mathaikutty , Ram K. Krishnamurthy , Martin Power
CPC classification number: G06F7/5443 , G06F7/4876 , G06F7/485 , G06F5/012
Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.
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公开(公告)号：US20190280693A1
公开(公告)日：2019-09-12
申请号：US16335092
申请日：2017-08-30
Applicant: Intel Corporation
Inventor： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC: H03K19/0185 , H03K3/037
Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.
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公开(公告)号：US10177765B2
公开(公告)日：2019-01-08
申请号：US15244839
申请日：2016-08-23
Applicant: Intel Corporation
Inventor： Steven K. Hsu , Amit Agarwal , Iqbal R. Rajwani , Simeon Realov , Ram K. Krishnamurthy
IPC: H03K19/00 , H03K19/0944 , H03K19/20
Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.
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Patent Agency Ranking
36.发明申请公开(公告)号：US20180189645A1
公开(公告)日：2018-07-05
申请号：US15394897
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： Gregory K. Chen , Raghavan Kumar , Huseyin Ekin Sumbul , Phil Knag , Ram K. Krishnamurthy
CPC classification number: G06N3/0635 , G06N3/0445 , G06N3/049 , G06N3/063
Abstract: In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.
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公开(公告)号：US20180145663A1
公开(公告)日：2018-05-24
申请号：US15860562
申请日：2018-01-02
Applicant: INTEL CORPORATION
Inventor： Amit Agarwal , Steven K. Hsu , Simeon Realov , Iqbal R. Rajwani , Ram K. Krishnamurthy
IPC: H03K3/3562 , H03K3/037
CPC classification number: H03K3/3562 , H03K3/0372 , H03K3/35625
Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
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公开(公告)号：US09965248B2
公开(公告)日：2018-05-08
申请号：US15296139
申请日：2016-10-18
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
CPC classification number: G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
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公开(公告)号：US20180091150A1
公开(公告)日：2018-03-29
申请号：US15277189
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC: H03K19/0185 , H03K3/037
CPC classification number: H03K19/018521 , H03K3/037 , H03K3/0372
Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.
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公开(公告)号：US20180069538A1
公开(公告)日：2018-03-08
申请号：US15260180
申请日：2016-09-08
Applicant: Intel Corporation
Inventor： Amit Agarwal , Steven K. Hsu , Ram K. Krishnamurthy
CPC classification number: H03K3/012 , H03K3/35625
Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.
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