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公开(公告)号：US10997771B2
公开(公告)日：2021-05-04
申请号：US16116158
申请日：2018-08-29
Applicant: Intel Corporation
Inventor： Travis Schluessler , Zack Waters , Michael Apodaca , Daniel Johnston , Jason Surprise , Prasoonkumar Surti , Subramaniam Maiyuran , Peter Doyle , Saurabh Sharma , Ankur Shah , Murali Ramadoss
Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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公开(公告)号：US20210035259A1
公开(公告)日：2021-02-04
申请号：US16930935
申请日：2020-07-16
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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公开(公告)号：US20200342662A1
公开(公告)日：2020-10-29
申请号：US16395717
申请日：2019-04-26
Applicant: Intel Corporation
Inventor： Justin DeCell , Saurabh Sharma , Subramaniam Maiyuran , Raghavendra Miyar , Jorge Garcia Pabon
Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
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公开(公告)号：US20200098167A1
公开(公告)日：2020-03-26
申请号：US16456645
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
Abstract: Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
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公开(公告)号：US10546362B2
公开(公告)日：2020-01-28
申请号：US15830860
申请日：2017-12-04
Applicant: Intel Corporation
Abstract: An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.
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Patent Agency Ranking
公开(公告)号：US10417730B2
公开(公告)日：2019-09-17
申请号：US15386111
申请日：2016-12-21
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge F. Garcia Pabon , Vikranth Vemulapalli , Chandra S. Gurram , Aditya Navale , Saurabh Sharma
Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.
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37.发明授权公开(公告)号：US10146691B2
公开(公告)日：2018-12-04
申请号：US15374630
申请日：2016-12-09
Applicant: INTEL CORPORATION
Inventor： Hashem Hashemi , Saurabh Sharma , Altug Koker
IPC: G06F12/16 , G06F12/0842
Abstract: One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.
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公开(公告)号：US20180218474A1
公开(公告)日：2018-08-02
申请号：US15830860
申请日：2017-12-04
Applicant: Intel Corporation
Abstract: An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.
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39.发明申请公开(公告)号：US20180165201A1
公开(公告)日：2018-06-14
申请号：US15374630
申请日：2016-12-09
Applicant: INTEL CORPORATION
Inventor： HASHEM HASHEMI , Saurabh Sharma , Altug Koker
IPC: G06F12/0842
CPC classification number: G06F12/0842 , G06F12/0886 , G06F12/0893 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041
Abstract: One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.
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公开(公告)号：US09846962B2
公开(公告)日：2017-12-19
申请号：US14865200
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam M. Maiyuran , Saurabh Sharma
CPC classification number: G06T15/30 , G06T11/40 , G06T15/005 , G06T15/80
Abstract: Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the Position Only Shading Pipe (POSH) pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.
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