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    Data distribution in an array of neural network cores
    32.
    发明授权
    Data distribution in an array of neural network cores 有权

    公开(公告)号：US11238347B2

    公开(公告)日：2022-02-01

    申请号：US16146632

    申请日：2018-09-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Brian Taba ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Pallab Datta ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  John V. Arthur ,  Dharmendra S. Modha ,  Steven K. Esser ,  Jennifer Klamo

    IPC分类号： G06N3/08 ,  G06F17/16 ,  G06N3/06 ,  G06N3/04

    摘要： Parallel processing among arrays of physical neural cores is provided. An array of neural cores is adapted to compute, in parallel, an output activation tensor of a neural network layer. A network is operatively connected to each of the neural cores. The output activation tensor is distributed across the neural cores. An input activation tensor is distributed across the neural cores. A weight tensor is distributed across the neural cores. Each neural core's computation comprises multiplying elements of a portion of the input activation tensor at that core with elements of a portion of the weight tensor at that core, and storing the summed products in a partial sum corresponding to an element of the output activation tensor. Each element of the output activation tensor is computed by accumulating all of the partial sums corresponding to that element via the network. The partial sums for each element of the output activation tensor are computed in a sequence of steps whose order is described by tracing a path through the weight tensor that visits every weight tensor element that contributes to any partial sum.

    COMPRESSED WEIGHT DISTRIBUTION IN NETWORKS OF NEURAL PROCESSORS
    33.
    发明申请
    COMPRESSED WEIGHT DISTRIBUTION IN NETWORKS OF NEURAL PROCESSORS 有权

    公开(公告)号：US20210209450A1

    公开(公告)日：2021-07-08

    申请号：US16733393

    申请日：2020-01-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Andrew S. Cassidy ,  Rathinakumar Appuswamy ,  John V. Arthur ,  Pallab Datta ,  Steve Esser ,  Myron D. Flickner ,  Dharmendra S. Modha ,  Jun Sawada

    IPC分类号： G06N3/063

    摘要： A neural inference chip includes a global weight memory; a neural core; and a network connecting the global weight memory to the at least one neural core. The neural core comprises a local weight memory. The local weight memory comprises a plurality of memory banks. Each of the plurality of memory banks is uniquely addressable by at least one index. The neural inference chip is adapted to store in the global weight memory a compressed weight block comprising at least one compressed weight matrix. The neural inference chip is adapted to transmit the compressed weight block from the global weight memory to the core via the network. The core is adapted to decode the at least one compressed weight matrix into a decoded weight matrix and store the decoded weight matrix in its local weight memory. The at core is adapted to apply the decoded weight matrix to a plurality of input activations to produce a plurality of output activations.

    TRANSFORM FOR A NEUROSYNAPTIC CORE CIRCUIT
    36.
    发明申请
    TRANSFORM FOR A NEUROSYNAPTIC CORE CIRCUIT 审中-公开

    公开(公告)号：US20190138883A1

    公开(公告)日：2019-05-09

    申请号：US15980612

    申请日：2018-05-15

    申请人： International Business Machines Corporation

    发明人： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

    IPC分类号： G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08

    摘要： Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

    Transform architecture for multiple neurosynaptic core circuits
    37.
    发明授权
    Transform architecture for multiple neurosynaptic core circuits 有权

    公开(公告)号：US10198690B2

    公开(公告)日：2019-02-05

    申请号：US15184917

    申请日：2016-06-16

    申请人： International Business Machines Corporation

    发明人： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06F17/16

    摘要： Embodiments of the present invention provide a method for feature extraction using multiple neurosynaptic core circuits including one or more input core circuits for receiving input and one or more output core circuits for generating output. The method comprises receiving a set of input data via the input core circuits, and extracting a first set of features from the input data using the input core circuits. Each feature of the first set of features is based on a subset of the input data. The method further comprises reordering the first set of features using the input core circuits, and generating a second set of features by combining the reordered first set of features using the output core circuits. The second set of features comprises a set of features with reduced correlation. Each feature of the second set of features is based on the entirety of said set of input data.

    TRANSFORM FOR A NEUROSYNAPTIC CORE CIRCUIT
    39.
    发明申请
    TRANSFORM FOR A NEUROSYNAPTIC CORE CIRCUIT 审中-公开
    神经细胞核心电路的变换

    公开(公告)号：US20170068884A1

    公开(公告)日：2017-03-09

    申请号：US15184880

    申请日：2016-06-16

    申请人： International Business Machines Corporation

    发明人： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

    IPC分类号： G06N3/063 ,  G06F17/16 ,  G06N3/08

    CPC分类号： G06N3/04 ,  G06F17/16 ,  G06N3/049 ,  G06N3/063 ,  G06N3/088

    摘要： Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

    摘要翻译： 本发明的实施例提供了一种用于特征提取的方法，包括产生用于神经突触核心电路的突触连接信息。 核心电路包括一个或多个电子神经元，一个或多个电子轴突，以及包括用于将神经元与轴突互连的多个突触装置的互连结构。 该方法还包括基于产生的突触连接信息来初始化互连结构，以及经由电子轴突接收的输入提取一组特征。 所提取的特征集包括具有降低的相关性的一组特征。