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    Memory device having different burst order addressing for read and write operations
    31.
    发明授权
    Memory device having different burst order addressing for read and write operations 有权
    具有用于读和写操作的不同突发顺序寻址的存储器件

    公开(公告)号：US06779074B2

    公开(公告)日：2004-08-17

    申请号：US09905004

    申请日：2001-07-13

    申请人： Jeffery W. Janzen

    发明人： Jeffery W. Janzen

    IPC分类号： G06F1200

    CPC分类号： G11C7/1018 ,  G11C7/1021 ,  G11C7/103 ,  G11C8/04

    摘要： An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

    摘要翻译： 寻址方案和相关硬件允许进行两种不同类型的访问，一种用于阅读，一种用于写入。 根据本发明构造的存储器件包括多个存储单元阵列。 提供外部设备用于从多个存储器单元读取信息并将信息写入到多个存储器单元中。 外围设备包括响应于某些地址位的排序电路，用于排序从多个阵列接收的位;以及地址定序器，用于在读取操作期间将某些地址位路由到重排序电路。 本发明的方法包括在从存储器件输出至少一个n位字之前，根据某些地址位中的信息重新排列从存储器阵列输出的n位字的块。

    System and method for decoding commands based on command signals and operating state
    32.
    发明授权
    System and method for decoding commands based on command signals and operating state 有权
    基于命令信号和操作状态对命令进行解码的系统和方法

    公开(公告)号：US08205055B2

    公开(公告)日：2012-06-19

    申请号：US12820877

    申请日：2010-06-22

    申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F13/16

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    System and method for optimizing interconnections of components in a multichip memory module
    33.
    发明授权
    System and method for optimizing interconnections of components in a multichip memory module 有权
    用于优化多芯片存储器模块中组件互连的系统和方法

    公开(公告)号：US07870329B2

    公开(公告)日：2011-01-11

    申请号：US11417389

    申请日：2006-05-03

    申请人： Jeffery W. Janzen

    发明人： Jeffery W. Janzen

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/1684 ,  G11C5/025 ,  G11C5/04

    摘要： An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

    摘要翻译： 装置和方法将存储器模块中的存储器件耦合到模块上的存储器集线器，使得从集线器传输到设备的信号具有大致相同的传播时间，而不管涉及哪个设备。 具体地，设备成对地布置在集线器周围，每对设备被定向成使得成对中的每个设备（例如数据总线信号）的功能信号组彼此相邻地定位在 模块。 这允许具有大致相同电特性的数据和控制地址总线在集线器和每个设备之间路由。 这种设备的物理布置允许模块的高速运行。 在一个示例中，集线器位于模块的中心，并且四个对设置在集线器周围的八个设备。

    System and method for decoding commands based on command signals and operating state
    34.
    发明授权
    System and method for decoding commands based on command signals and operating state 有权
    基于命令信号和操作状态对命令进行解码的系统和方法

    公开(公告)号：US07757061B2

    公开(公告)日：2010-07-13

    申请号：US11121868

    申请日：2005-05-03

    申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F13/36

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    Method and system for reducing the peak current in refreshing dynamic random access memory devices
    37.
    发明授权
    Method and system for reducing the peak current in refreshing dynamic random access memory devices 失效
    刷新动态随机存取存储器件中降低峰值电流的方法和系统

    公开(公告)号：US07349277B2

    公开(公告)日：2008-03-25

    申请号：US11431371

    申请日：2006-05-09

    申请人： Thomas H. Kinsley ,  Jeffery W. Janzen

    发明人： Thomas H. Kinsley ,  Jeffery W. Janzen

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

    摘要： A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

    摘要翻译： 动态随机存取存储器件包括用延迟值编程的模式寄存器。 在一些实施例中，偏移代码也存储在存储器件中。 存储器件使用延迟值，该延迟值可以被添加到偏移代码或乘以偏移代码，以延迟接收的自动刷新或自刷新命令的启动。 可以为系统中的大量动态随机存取存储器件提供不同的延迟值和可能的偏移代码，使得存储器件不是都响应于自动刷新或自刷新命令而同时执行刷新 同时存储设备。 结果，由自动刷新命令或自刷新命令产生的存储器件所绘制的峰值电流保持在较低的值。

    Sequential nibble burst ordering for data
    38.
    发明授权
    Sequential nibble burst ordering for data 失效
    数据的顺序半字节排序

    公开(公告)号：US07085912B2

    公开(公告)日：2006-08-01

    申请号：US10778257

    申请日：2004-02-13

    申请人： Jeffery W. Janzen

    发明人： Jeffery W. Janzen

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1033

    摘要： Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.

    摘要翻译： 操作由存储器单元的多个阵列和用于向存储器单元读取和写入信息的外围设备的存储器件的操作方法。 一种方法包括响应于地址位从多个存储器阵列输出两个1/2位预取步骤中的n位字。 另一种方法包括从存储器阵列预取字的第一部分，以及从存储器阵列预取字的第二部分，第一和第二部分由地址位确定。 另一种方法包括在至少两个预取操作中从存储器阵列中读出一个字，其中预取操作的顺序由地址位控制。

    Sequential nibble burst ordering for data
    39.
    发明授权
    Sequential nibble burst ordering for data 失效
    数据的顺序半字节排序

    公开(公告)号：US06775759B2

    公开(公告)日：2004-08-10

    申请号：US10008710

    申请日：2001-12-07

    申请人： Jeffery W. Janzen

    发明人： Jeffery W. Janzen

    IPC分类号： G06F1200

    CPC分类号： G11C7/1033

    摘要： A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written in response to another portion of the address information. Methods of operating such a memory device including outputting or reading a word from a memory array in two prefetch steps or operations are also disclosed.

    摘要翻译： 存储器装置由存储器单元的多个阵列和用于向存储器单元读取和写入信息的外围设备组成。 外围设备包括响应于用于识别地址的地址信息的第一部分的解码电路，并且还响应于用于识别订单的地址信息的第二部分。 该地址可以是读取地址或写入地址，并且该顺序可以分别是读取数据或写入数据的顺序。 外围设备还可以包括读序列器电路或写定序器电路和读定序器电路，用于根据地址信息的另一部分重新排序要读或写的位。 还公开了这样的存储装置的操作方法，包括在两个预取步骤或操作中从存储器阵列输出或读出一个字。

    Dram active termination control
    40.
    发明授权
    Dram active termination control 有权
    戏剧活动终止控制

    公开(公告)号：US06538951B1

    公开(公告)日：2003-03-25

    申请号：US09941649

    申请日：2001-08-30

    申请人： Jeffery W. Janzen ,  Brent Keeth

    发明人： Jeffery W. Janzen ,  Brent Keeth

    IPC分类号： G11C800

    CPC分类号： G11C11/4093 ,  G11C7/10

    摘要： A method and apparatus for active termination control of a memory module is disclosed. A memory controller provides a single active termination control line per memory module which is used to control memory devices on both sides of a module. The active termination control signal is active for all write functions to the memory devices on the modules. A device read signal generated by the memory devices on one side of the module disables the active termination control signal for memory devices on both sides of the module to enable faster turnarounds between write and read operations.

    摘要翻译： 公开了一种用于存储器模块的主动终止控制的方法和装置。 存储器控制器为每个存储器模块提供单个有源终端控制线，其用于控制​​模块两侧的存储器件。 主动终止控制信号对于模块上的存储器件的所有写入功能都有效。 由模块一侧的存储器件产生的器件读取信号会禁用模块两侧存储器件的有效终止控制信号，从而实现写操作和读操作之间更快的周转。