公开(公告)号：US20120243323A1

公开(公告)日：2012-09-27

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US08208310B2

公开(公告)日：2012-06-26

申请号：US12773701

申请日：2010-05-04

申请人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

发明人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/3418

摘要： Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

摘要翻译： 通过匹配在读取期间发生的信道耦合量与验证期间发生的信道耦合，可以减轻非易失性存储的验证和读取期间的信道耦合效应。 在验证和读取期间，所有位线都可以一起读取。 在一个实施例中，当验证多个编程状态中的每一个时，在位线上建立第一偏置条件。 在验证每个状态时可以建立单独的第一偏置条件集合。 偏置位线可以基于位线上的非易失性存储元件被编程的状态。 为正在读取的每个状态建立一组单独的第二偏置条件。 给定状态的第二偏置条件基本上与给定状态的第一偏置条件相匹配。

公开(公告)号：US08130551B2

公开(公告)日：2012-03-06

申请号：US12751265

申请日：2010-03-31

申请人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

发明人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/14 ,  G11C16/3436

摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.

摘要翻译： 用于非易失性存储器的擦除操作包括第一和第二相。 第一阶段将一系列电压脉冲施加到衬底，其中每个擦除脉冲之后是验证操作。 验证操作使用从最终期望的阈值电压电平偏移的验证电平。 擦除脉冲以幅度升高直到达到最大电平，此时施加最大电平的附加擦除脉冲。 当验证操作通过时，第一阶段结束。 第二阶段施加一个或多个额外的擦除脉冲，其幅度高于第一阶段中的最后一个擦除脉冲，并且其后跟无验证操作。 这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写擦除耐久性，同时仍然实现期望的深度擦除。

公开(公告)号：US20110273935A1

公开(公告)日：2011-11-10

申请号：US12773701

申请日：2010-05-04

申请人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

发明人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/3418

摘要： Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

摘要翻译： 通过匹配在读取期间发生的信道耦合量与验证期间发生的信道耦合，可以减轻非易失性存储的验证和读取期间的信道耦合效应。 在验证和读取期间，所有位线都可以一起读取。 在一个实施例中，当验证多个编程状态中的每一个时，在位线上建立第一偏置条件。 在验证每个状态时可以建立单独的第一偏置条件集合。 偏置位线可以基于位线上的非易失性存储元件被编程的状态。 为正在读取的每个状态建立一组单独的第二偏置条件。 给定状态的第二偏置条件基本上与给定状态的第一偏置条件相匹配。

公开(公告)号：US20110255345A1

公开(公告)日：2011-10-20

申请号：US12762342

申请日：2010-04-18

申请人： Yingda Dong ,  Shih-Chung Lee ,  Ken Oowada

发明人： Yingda Dong ,  Shih-Chung Lee ,  Ken Oowada

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US20110170358A1

公开(公告)日：2011-07-14

申请号：US12638853

申请日：2009-12-15

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US20110051517A1

公开(公告)日：2011-03-03

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Le ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Le ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

公开(公告)号：US07719902B2

公开(公告)日：2010-05-18

申请号：US12126375

申请日：2008-05-23

申请人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427

摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.

摘要翻译： 在非易失性存储器中改善通道增强以减少程序干扰。 预充电模块电压源用于在编程操作期间对位线进行预充电。 预充电模块电压源通过位线耦合到衬底通道以升高通道。 通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。 为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。 导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

公开(公告)号：US07706189B2

公开(公告)日：2010-04-27

申请号：US11753963

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US07656703B2

公开(公告)日：2010-02-02

申请号：US11753958

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，使得编程将被禁止。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。