公开(公告)号：US08456915B2

公开(公告)日：2013-06-04

申请号：US13436805

申请日：2012-03-30

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US20120188824A1

公开(公告)日：2012-07-26

申请号：US13436805

申请日：2012-03-30

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US08174895B2

公开(公告)日：2012-05-08

申请号：US12638853

申请日：2009-12-15

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US20110170358A1

公开(公告)日：2011-07-14

申请号：US12638853

申请日：2009-12-15

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US07961511B2

公开(公告)日：2011-06-14

申请号：US11535452

申请日：2006-09-26

申请人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

发明人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.

摘要翻译： 描述了将非易失性存储器单元编程到最终编程状态的混合方法。 所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。 混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程 单元格到最终编程状态。 另外，所描述的方法对于编程多级芯片是特别有利的。

公开(公告)号：US20080084761A1

公开(公告)日：2008-04-10

申请号：US11535452

申请日：2006-09-26

申请人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

发明人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.

摘要翻译： 描述了将非易失性存储器单元编程到最终编程状态的混合方法。 所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。 混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程 单元格到最终编程状态。 另外，所描述的方法对于编程多级芯片是特别有利的。

公开(公告)号：US08472257B2

公开(公告)日：2013-06-25

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US20120314499A1

公开(公告)日：2012-12-13

申请号：US13155323

申请日：2011-06-07

申请人： Jiahui Yuan ,  Yingda Dong ,  Charles Kwong

发明人： Jiahui Yuan ,  Yingda Dong ,  Charles Kwong

IPC分类号： G11C16/26 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

摘要翻译： 确定并优化循环存储器的第一个读通过电压。 为一个或多个管芯确定一个或多个启动读通过电压。 该系统基于编程/擦除擦除周期的数量，第一读取通过电压和相应的启动读取通过电压来动态地计算当前的读取通过电压。 使用计算出的电流读通过电压从一个或多个非易失性存储元件读取数据。

公开(公告)号：US08144511B2

公开(公告)日：2012-03-27

申请号：US12544113

申请日：2009-08-19

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

公开(公告)号：US08081514B2

公开(公告)日：2011-12-20

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。