公开(公告)号：US08208310B2

公开(公告)日：2012-06-26

申请号：US12773701

申请日：2010-05-04

申请人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

发明人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/3418

摘要： Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

摘要翻译： 通过匹配在读取期间发生的信道耦合量与验证期间发生的信道耦合，可以减轻非易失性存储的验证和读取期间的信道耦合效应。 在验证和读取期间，所有位线都可以一起读取。 在一个实施例中，当验证多个编程状态中的每一个时，在位线上建立第一偏置条件。 在验证每个状态时可以建立单独的第一偏置条件集合。 偏置位线可以基于位线上的非易失性存储元件被编程的状态。 为正在读取的每个状态建立一组单独的第二偏置条件。 给定状态的第二偏置条件基本上与给定状态的第一偏置条件相匹配。

公开(公告)号：US20110273935A1

公开(公告)日：2011-11-10

申请号：US12773701

申请日：2010-05-04

申请人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

发明人： Yingda Dong ,  Yan Li ,  Cynthia Hsu

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/3418

摘要： Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

摘要翻译： 通过匹配在读取期间发生的信道耦合量与验证期间发生的信道耦合，可以减轻非易失性存储的验证和读取期间的信道耦合效应。 在验证和读取期间，所有位线都可以一起读取。 在一个实施例中，当验证多个编程状态中的每一个时，在位线上建立第一偏置条件。 在验证每个状态时可以建立单独的第一偏置条件集合。 偏置位线可以基于位线上的非易失性存储元件被编程的状态。 为正在读取的每个状态建立一组单独的第二偏置条件。 给定状态的第二偏置条件基本上与给定状态的第一偏置条件相匹配。

公开(公告)号：US08472257B2

公开(公告)日：2013-06-25

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US20100329002A1

公开(公告)日：2010-12-30

申请号：US12490557

申请日：2009-06-24

申请人： Yingda Dong ,  Cynthia Hsu

发明人： Yingda Dong ,  Cynthia Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/3418

摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N1 and a number N2>N1 of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure can involve using a higher pass voltage, or abandoning programming of an upper page of data or an entire block. In some cases, programming continues with no precautionary measure.

摘要翻译： 在编程操作期间，在非易失性存储系统中通过确定一组存储元件对编程干扰的敏感度并在需要时采取相应的预防措施来减少程序干扰发生的可能性，从而减少了程序干扰。 在下一页数据的编程期间，通过对被编程到特定状态的存储元件进行跟踪，并且确定需要数量N1和数N2的多个编程脉冲来确定该组存储元件的自然阈值电压分布 > N1的存储元素达到特定状态。 温度和字线位置也可用于确定编程干扰的敏感度。 预防措施可以涉及使用较高的通过电压，或放弃对数据的上部页面或整个块的编程。 在某些情况下，方案继续采取预防措施。

公开(公告)号：US20120243323A1

公开(公告)日：2012-09-27

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US07916533B2

公开(公告)日：2011-03-29

申请号：US12490557

申请日：2009-06-24

申请人： Yingda Dong ,  Cynthia Hsu

发明人： Yingda Dong ,  Cynthia Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/3418

摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N1 and a number N2>N1 of the storage elements to reach the particular state. Temperature and word line position can also be used to determine the susceptibility to program disturb. A precautionary measure can involve using a higher pass voltage, or abandoning programming of an upper page of data or an entire block. In some cases, programming continues with no precautionary measure.

摘要翻译： 在编程操作期间，在非易失性存储系统中通过确定一组存储元件对编程干扰的敏感度并在需要时采取相应的预防措施来减少程序干扰发生的可能性，从而减少了程序干扰。 在下一页数据的编程期间，通过对被编程到特定状态的存储元件进行跟踪，并且确定需要数量N1和数N2的多个编程脉冲来确定该组存储元件的自然阈值电压分布 > N1的存储元素达到特定状态。 温度和字线位置也可用于确定编程干扰的敏感度。 预防措施可以涉及使用较高的通过电压，或放弃对数据的上部页面或整个块的编程。 在某些情况下，方案继续采取预防措施。

公开(公告)号：US20120314499A1

公开(公告)日：2012-12-13

申请号：US13155323

申请日：2011-06-07

申请人： Jiahui Yuan ,  Yingda Dong ,  Charles Kwong

发明人： Jiahui Yuan ,  Yingda Dong ,  Charles Kwong

IPC分类号： G11C16/26 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

摘要翻译： 确定并优化循环存储器的第一个读通过电压。 为一个或多个管芯确定一个或多个启动读通过电压。 该系统基于编程/擦除擦除周期的数量，第一读取通过电压和相应的启动读取通过电压来动态地计算当前的读取通过电压。 使用计算出的电流读通过电压从一个或多个非易失性存储元件读取数据。

公开(公告)号：US08144511B2

公开(公告)日：2012-03-27

申请号：US12544113

申请日：2009-08-19

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

公开(公告)号：US08081514B2

公开(公告)日：2011-12-20

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

公开(公告)号：US20110249504A1

公开(公告)日：2011-10-13

申请号：US12757399

申请日：2010-04-09

申请人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622

摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

摘要翻译： 在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。 在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。 该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。 集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。 在子脉冲组之后执行验证操作。 每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。