公开(公告)号：US20090108355A1

公开(公告)日：2009-04-30

申请号：US12348391

申请日：2009-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/092

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US09040929B2

公开(公告)日：2015-05-26

申请号：US13561671

申请日：2012-07-30

申请人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： G01T1/24 ,  H01L31/115 ,  H01L27/146

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。 由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

公开(公告)号：US08980667B2

公开(公告)日：2015-03-17

申请号：US13566324

申请日：2012-08-03

申请人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

发明人： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC分类号： H01L31/101 ,  H01L31/11 ,  H01L27/14

CPC分类号： G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

摘要： A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

摘要翻译： 形成传感器的方法包括形成与基底基板接触的基底区域屏障。 基区域屏障包括具有与基底衬底相同的掺杂剂导电性的单晶半导体。 发射极和集电极形成为与基极区势垒接触并在相对侧上形成双极结型晶体管。 集电极，发射极和基极区势垒被平坦化以形成与基底衬底相对的电平表面，使得当电平表面暴露于电荷时，在双极结型晶体管的操作期间测量电荷。

公开(公告)号：US08492794B2

公开(公告)日：2013-07-23

申请号：US13048366

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L29/66

CPC分类号： H01L29/737 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

公开(公告)号：US07700993B2

公开(公告)日：2010-04-20

申请号：US11935143

申请日：2007-11-05

申请人： Jin Cai ,  Tak H. Ning ,  John M. Safran

发明人： Jin Cai ,  Tak H. Ning ,  John M. Safran

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  G11C16/0433 ,  G11C16/10 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881

摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.

摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。 厚栅极电介质层基本上比薄栅极电介质层厚。 连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。 存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。

公开(公告)号：US08927380B2

公开(公告)日：2015-01-06

申请号：US13369261

申请日：2012-02-08

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66234 ,  H01L21/761 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/73

摘要： A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

公开(公告)号：US08531001B2

公开(公告)日：2013-09-10

申请号：US13158419

申请日：2011-06-12

申请人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Robert H. Dennard ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/082

摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

摘要翻译： 示例性实施例是互补晶体管反相器电路。 电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。 横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。 横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

公开(公告)号：US08415744B2

公开(公告)日：2013-04-09

申请号：US13344006

申请日：2012-01-05

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

摘要翻译： 本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置 ）电路，其位于绝缘体上硅（SOI）衬底上。 具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。 例如，可以使用正的衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负的衬底偏置电压可以用于增加n-FET的阈值电压，但是 减少p-FET的电流。 此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

公开(公告)号：US20090256204A1

公开(公告)日：2009-10-15

申请号：US12099879

申请日：2008-04-09

申请人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

发明人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

IPC分类号： H01L29/786

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/0722

摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

摘要翻译： 绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。 源区具有第一导电类型。 体区具有第二导电类型并且位于源区和漏区之间。 源极横向双极晶体管包括基极，集电极和发射极。 硅化物区将基底连接到收集器。 发射器是身体区域。 集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

公开(公告)号：US20090114971A1

公开(公告)日：2009-05-07

申请号：US11935143

申请日：2007-11-05

申请人： Jin Cai ,  Tak H. Ning ,  John M. Safran

发明人： Jin Cai ,  Tak H. Ning ,  John M. Safran

IPC分类号： H01L27/092 ,  H01L27/12

CPC分类号： H01L21/823857 ,  G11C16/0433 ,  G11C16/10 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881

摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.

摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。 厚栅极电介质层基本上比薄栅极电介质层厚。 连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。 存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。