公开(公告)号：US08859302B2

公开(公告)日：2014-10-14

申请号：US13036243

申请日：2011-02-28

申请人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

发明人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

IPC分类号： H01L21/66 ,  G11C11/412 ,  H01L27/11 ,  H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66

CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/66833 ,  H01L29/786 ,  H01L29/792

摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

摘要翻译： 一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。 可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。 注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

公开(公告)号：US08558282B1

公开(公告)日：2013-10-15

申请号：US13607672

申请日：2012-09-08

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/331

CPC分类号： H01L29/6625 ,  H01L29/161 ,  H01L29/735

摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

公开(公告)号：US20130260526A1

公开(公告)日：2013-10-03

申请号：US13605253

申请日：2012-09-06

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/8222

CPC分类号： H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

公开(公告)号：US08526220B2

公开(公告)日：2013-09-03

申请号：US13158420

申请日：2011-06-12

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： G11C11/00

CPC分类号： H01L27/082 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/1203

摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

摘要翻译： 示例性实施例是包括SOI衬底的存储单元。 在SOI衬底上制造第一和第二组横向双极晶体管。 第一和第二组横向双极晶体管电耦合以形成两个反相器。 逆变器交叉耦合以形成存储元件。

公开(公告)号：US20130168821A1

公开(公告)日：2013-07-04

申请号：US13343688

申请日：2012-01-04

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： H01L27/082 ,  H01L21/328 ,  H01L29/70

CPC分类号： H01L27/082 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735

摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

摘要翻译： 一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。 在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

公开(公告)号：US20120314485A1

公开(公告)日：2012-12-13

申请号：US13158420

申请日：2011-06-12

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： G11C11/34 ,  H01L21/8222 ,  G11C11/00

CPC分类号： H01L27/082 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/1203

摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

摘要翻译： 示例性实施例是包括SOI衬底的存储单元。 在SOI衬底上制造第一和第二组横向双极晶体管。 第一和第二组横向双极晶体管电耦合以形成两个反相器。 逆变器交叉耦合以形成存储元件。

公开(公告)号：US08314463B2

公开(公告)日：2012-11-20

申请号：US12542879

申请日：2009-08-18

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

公开(公告)号：US20120235151A1

公开(公告)日：2012-09-20

申请号：US13048342

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/737 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66265

摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

摘要翻译： 水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。 在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。 在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。 在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。 在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

公开(公告)号：US20110115553A1

公开(公告)日：2011-05-19

申请号：US12619285

申请日：2009-11-16

申请人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

发明人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

IPC分类号： G05F1/10 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7841

摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

摘要翻译： 提供具有至少一个可编程电浮动背板的SOI CMOS结构。 每个电浮动背板均可单独编程。 可以通过将电子注入每个导电浮动背板来进行编程。 编程的擦除可以通过将电子穿过浮动背板来实现。 两个装置中的至少一个可以完成电浮动背栅的编程。 这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。 使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

公开(公告)号：US07808039B2

公开(公告)日：2010-10-05

申请号：US12099879

申请日：2008-04-09

申请人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

发明人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

IPC分类号： H01L27/088

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/0722

摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

摘要翻译： 绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。 源区具有第一导电类型。 体区具有第二导电类型并且位于源区和漏区之间。 源极横向双极晶体管包括基极，集电极和发射极。 硅化物区将基底连接到收集器。 发射器是身体区域。 集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。