公开(公告)号：US5847428A

公开(公告)日：1998-12-08

申请号：US761132

申请日：1996-12-06

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed. Each time, the implants are performed with a lower energy and with a lower dosage so as to grade the junction with lighter concentrations and energies as the implant areas approach the channel. Reversing the implantation process enables high-temperature thermal anneals required for high-concentration low-diffusivity dopants to be performed first. The LDD implant comprises dopants of lower concentration and higher diffusivity requiring lower temperature anneals. Performing lower temperature anneals later in the sequence affords a lessened opportunity for undesirable short-channel effects.

摘要翻译： 晶体管具有渐变源极/漏极结。 在栅极导体上依次形成至少两个电介质间隔物。 相邻的电介质间隔物具有不同的蚀刻特性。 离子注入沿着至少两个电介质间隔物的形成，以将掺杂剂引入到晶体管的源极/漏极区域中。 离子植入物根据电介质间隔物的厚度被放置在与栅极导体间隔距离的不同位置。 随着植入物从通道进一步引入，植入物剂量和能量增加。 在第二实施例中，以相反的顺序执行离子注入。 电介质垫片预先存在于栅极导体的侧壁表面上。 依次移除间隔物，然后离子注入。 使用蚀刻剂来攻击待移除的间隔物，而不是将垫片下移到被去除的间隔物。 每次，植入物以较低的能量和较低的剂量进行，以便随着植入区域接近通道而将结点分级为较轻的浓度和能量。 倒置注入工艺可以实现高浓度低扩散性掺杂剂首先要求的高温热退火。 LDD植入物包含较低浓度和较高扩散系数的掺杂剂，需要较低的温度退火。 在该顺序的稍后进行较低的温度退火可以减少不期望的短通道效应的机会。

公开(公告)号：US5844276A

公开(公告)日：1998-12-01

申请号：US760462

申请日：1996-12-06

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC分类号： H01L27/092 ,  H01L21/823814 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

摘要翻译： 提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。 首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。 首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。 与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。 通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

公开(公告)号：US5770485A

公开(公告)日：1998-06-23

申请号：US811417

申请日：1997-03-04

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L21/00 ,  H01L21/425

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/7835

摘要： An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability. A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate. The semiconductor substrate has a source region adjacent to a first side of the gate electrode and has a drain region adjacent to a second side of the gate electrode. The amorphous implant layer is self-aligned with the source mask and extends through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate. The method further includes the step of implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate. The source implant layer extends a shallower depth into the semiconductor substrate than the amorphous implant layer.

摘要翻译： 执行非晶化的植入物以阻止源极和漏极区域中的离子的扩散。 通过延迟这些区域中的离子的扩散，有利地在晶片的硅区域中产生较浅的结。 如果在晶体管的源极和漏极两侧进行非晶化注入，则可以获得漏电流的轻微降低。 然而，由于源极区域是具有非常浅的结的低电压区域，所以在n沟道区域和p沟道区域中形成具有改进的性能和可靠性的MOSFET。 一种制造集成电路的方法包括在半导体衬底上形成栅电极，形成在半导体衬底的漏极区域上延伸的源极掩模，以及将注入物质注入到半导体衬底的源极区域中以形成无定形注入层 的半导体衬底。 半导体衬底具有与栅电极的第一侧相邻的源极区，并且具有与栅电极的第二侧相邻的漏极区。 非晶注入层与源极掩模自对准并延伸穿过半导体衬底的暴露区域和半导体衬底的源极区域。 该方法还包括将源植入物植入半导体衬底的暴露区域和半导体衬底的源极区域以形成半导体衬底的源极注入层的步骤。 源极注入层比无定形植入层将比较深的深度延伸到半导体衬底中。

公开(公告)号：US5710054A

公开(公告)日：1998-01-20

申请号：US703273

申请日：1996-08-26

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L21/265 ,  H01L21/385

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/2257 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.

摘要翻译： 公开了一种在IGFET中形成浅结的方法。 该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁 绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。 扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

公开(公告)号：US06372588B2

公开(公告)日：2002-04-16

申请号：US08837523

申请日：1997-04-21

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/2256 ,  H01L21/32155 ,  H01L29/665

摘要： A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

摘要翻译： 公开了使用固相扩散制造IGFET的方法。 该方法包括在半导体衬底中提供器件区域，在器件区域上形成栅极绝缘体，在栅极绝缘体上形成栅极，在栅极和器件区域上形成绝缘层，在其上形成重掺杂扩散源层 绝缘层，并且通过固相扩散将掺杂剂从扩散源层驱动通过绝缘层进入栅极和器件区域，从而大量掺杂栅极并在器件区域中形成重掺杂的源极和漏极。 优选地，栅极和扩散源层是多晶硅，栅绝缘体和绝缘层是二氧化硅，掺杂剂是硼或硼物质，并且掺杂剂为栅极，源极和漏极提供基本上所有的P型掺杂，从而提供浅 通道结并且减少或消除从孔进入衬底的硼渗透。

公开(公告)号：US06259142B1

公开(公告)日：2001-07-10

申请号：US09056837

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L2976

CPC分类号： H01L29/66484 ,  H01L29/7831

摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.

摘要翻译： 具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。 交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。 源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

公开(公告)号：US06204148B1

公开(公告)日：2001-03-20

申请号：US09329843

申请日：1999-06-11

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L2176

CPC分类号： H01L29/66583

摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.

摘要翻译： 部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。 第一层位于衬底的至少一部分上方。 多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。 第一开口具有由多个侧壁限定的第一宽度。 多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。 第二开口具有第二宽度，第二宽度小于第一宽度。 部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。 在工艺层的至少一部分上方形成多晶硅层。 在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。 通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

公开(公告)号：US06201278B1

公开(公告)日：2001-03-13

申请号：US09028896

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31062

CPC分类号： H01L29/7834 ,  H01L29/66621

摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

摘要翻译： 公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。 形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在 基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极 电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与 栅电极。 有利地，沟道长度明显小于沟槽长度。

公开(公告)号：US6100146A

公开(公告)日：2000-08-08

申请号：US739595

申请日：1996-10-30

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L29/66621

摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

摘要翻译： 公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。 形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在 基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极 电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与 栅电极。 有利地，沟道长度明显小于沟槽长度。

公开(公告)号：US06080629A

公开(公告)日：2000-06-27

申请号：US837579

申请日：1997-04-21

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28035

摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.

摘要翻译： 将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。 注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。 如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。 栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。 此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。 每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。 可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。