公开(公告)号：US07969220B2

公开(公告)日：2011-06-28

申请号：US12491567

申请日：2009-06-25

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.

Abstract translation: 延迟电路包括第一和第二选择性延迟级，每个延迟阶段包括多个单位延迟单元以延迟施加到其上的信号; 以及延迟控制单元，被配置为响应于第一和第二选择信号的代码组合，选择性地将输入信号施加到第一选择延迟级或第二选择性延迟级，并产生输出信号。

公开(公告)号：US20110128794A1

公开(公告)日：2011-06-02

申请号：US12649021

申请日：2009-12-29

Applicant: Hyun-Su Yoon ,  Jong-Chern Lee

Inventor： Hyun-Su Yoon ,  Jong-Chern Lee

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2272

Abstract: An apparatus for controlling an operation timing in a semiconductor memory device, comprising: a shift information generator configured to generate shift information based on data path delay information and latency information; and a shift register configured to shift a command based on the shift information and produce a shifted command to control an operation timing.

Abstract translation: 一种用于控制半导体存储器件中的操作定时的装置，包括：移位信息发生器，被配置为基于数据路径延迟信息和等待时间信息产生移位信息; 以及移位寄存器，被配置为基于移位信息移位命令，并产生移位的命令以控制操作定时。

公开(公告)号：US20100290263A1

公开(公告)日：2010-11-18

申请号：US12495269

申请日：2009-06-30

Applicant: Je-Yoon Kim ,  Jong-Chern Lee

Inventor： Je-Yoon Kim ,  Jong-Chern Lee

IPC: G11C19/00 ,  G11C7/00

CPC classification number: G11C19/00

Abstract: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.

Abstract translation: 用于控制读周期的电路包括被配置为依次移位读信号的多个移位级; 以及激活单元，被配置为通过对所述多个移位级的输出信号执行逻辑运算来激活表示读取周期的读取周期信号，其中所述多个移位级被配置为将所读取的信号顺序地移位一段时间 对应于突发设置信息。

公开(公告)号：US08581369B2

公开(公告)日：2013-11-12

申请号：US13620404

申请日：2012-09-14

Applicant: Jun-Gi Choi ,  Jong-Chern Lee

Inventor： Jun-Gi Choi ,  Jong-Chern Lee

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

Abstract translation: 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US08300486B2

公开(公告)日：2012-10-30

申请号：US12650073

申请日：2009-12-30

Applicant: Je-Yoon Kim ,  Jong-Chern Lee

Inventor： Je-Yoon Kim ,  Jong-Chern Lee

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40626

Abstract: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.

Abstract translation: 半导体存储装置的温度检测电路包括固定周期振荡器，温度可变信号发生单元和计数单元。 振荡器被配置为当启用使能信号时产生固定周期振荡器信号。 温度可变信号发生单元被配置为当使能信号被使能时，产生其使能间隔基于温度变化而变化的温度可变信号。 计数单元被配置为在温度可变信号的使能间隔期间对振荡器信号进行计数，以产生温度信息信号。

公开(公告)号：US20110291266A1

公开(公告)日：2011-12-01

申请号：US12833436

申请日：2010-07-09

Applicant: Sin-Hyun Jin ,  Jong-Chern Lee

Inventor： Sin-Hyun Jin ,  Jong-Chern Lee

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract translation: 具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。 半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径 到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

公开(公告)号：US20110158024A1

公开(公告)日：2011-06-30

申请号：US12650594

申请日：2009-12-31

Applicant: Dae-Suk KIM ,  Jong-Chern Lee

Inventor： Dae-Suk KIM ,  Jong-Chern Lee

IPC: G11C7/00 ,  G11C8/00 ,  G11C8/08

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

Abstract translation: 半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址， 刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

公开(公告)号：US20110156767A1

公开(公告)日：2011-06-30

申请号：US12755949

申请日：2010-04-07

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/07

Abstract: A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.

Abstract translation: 延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。 延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。 编码单元被配置为对延迟脉冲进行编码并输出代码值。 延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。 延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

公开(公告)号：US20110156766A1

公开(公告)日：2011-06-30

申请号：US12753442

申请日：2010-04-02

Applicant: Seung-Joon AHN ,  Jong-Chern Lee

Inventor： Seung-Joon AHN ,  Jong-Chern Lee

IPC: H03L7/00 ,  H03L7/06

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

Abstract translation: 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US20110103164A1

公开(公告)日：2011-05-05

申请号：US12647196

申请日：2009-12-24

Applicant: Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

Inventor： Jae-Woong YUN ,  Jong-Chern Lee ,  Hee-Jin Byun

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/40 ,  G11C2029/2602

Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.

Abstract translation: 半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路 被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到 芯片。