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公开(公告)号：US20130024541A1
公开(公告)日：2013-01-24
申请号：US13187800
申请日：2011-07-21
IPC分类号： G06F15/16
CPC分类号： H04L47/39 , H04L47/15 , H04L47/26 , H04L47/263 , H04L47/266 , H04L47/34 , H04L47/6205
摘要： Techniques are provided for sending request messages to destination nodes. Destination nodes may be indicated as unresolved. Request messages are sent to destination nodes indicated as unresolved.
摘要翻译： 提供了向目标节点发送请求消息的技术。 目标节点可能被指示为未解决。 请求消息被发送到未解析的目标节点。
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公开(公告)号：US20110211591A1
公开(公告)日：2011-09-01
申请号：US12714215
申请日：2010-02-26
IPC分类号： H04J3/24
摘要： A system comprises a processor, a reassembly buffer that receives mini-packets, and at least one data structure that comprises bits. The bits indicate the presence or absence of each of the mini-packets in the reassembly buffer and further indicate whether one of the mini-packets is a final mini-packet in a series of the mini-packets. The processor uses the bits to determine whether all mini-packets forming the series are present in the reassembly buffer. As a result of the determination, the processor causes the series to be read from the reassembly buffer.
摘要翻译： 系统包括处理器，接收小分组的重组缓冲器，以及包括位的至少一个数据结构。 这些位表示重新组装缓冲器中每个微型分组的存在或不存在，并进一步指示微型分组中的一个是一系列小分组中的最终小分组。 处理器使用这些位来确定构成该系列的所有迷你包是否存在于重新组装缓冲器中。 作为确定的结果，处理器使得从重新组装缓冲器读取串联。
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33.发明授权Program control flow conditioned on presence of requested data in cache memory 失效程序控制流程以高速缓冲存储器中所请求数据的存在为条件公开(公告)号：US06925535B2
公开(公告)日：2005-08-02
申请号：US09942154
申请日：2001-08-29
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3842 , G06F9/3861
摘要： Method and apparatus for conditioning program control flow on the presence of requested data in a cache memory. In a data processing system that includes a cache memory and a system memory coupled to a processor, in various embodiments program control flow is conditionally changed based on whether the data referenced in an instruction are present in the cache memory. When an instruction that includes a data reference and an alternate control path is executed, the control flow of the program is changed in accordance with the alternate control path if the referenced data are not present in the cache memory. The alternate control path is either explicitly specified or implicit in the instruction.
摘要翻译： 用于在高速缓冲存储器中存在所请求的数据时调节程序控制流的方法和装置。 在包括高速缓冲存储器和耦合到处理器的系统存储器的数据处理系统中，在各种实施例中，基于指令中引用的数据是否存在于高速缓冲存储器中，有条件地改变程序控制流程。 当执行包括数据参考和替代控制路径的指令时，如果所引用的数据不存在于高速缓冲存储器中，则根据备用控制路径改变程序的控制流程。 替代控制路径在指令中被明确指定或隐含。
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34.发明授权Method for allowing distributed high performance coherent memory with full error containment 有权允许分布式高性能相干存储器具有全错误容错的方法公开(公告)号：US06651193B1
公开(公告)日：2003-11-18
申请号：US09562589
申请日：2000-04-29
申请人： Kent A. Dickey , Michael L. Ziegler
发明人： Kent A. Dickey , Michael L. Ziegler
IPC分类号： G06F1100
CPC分类号： G06F11/0796 , G06F11/004 , G06F11/0724 , G06F11/0772
摘要： The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set, any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.
摘要翻译： 本发明提供一种确保能够具有大的可扩展性的基于分组的系统中的错误容纳的方法和系统。 在操作中，错误位与每个数据包一起行进，并且如果该位被置位，则接收该数据包的任何设备用于包含该数据包。 因此，错误消息仅传送到错误数据的一个位置，并且不会在不受错误影响的位置停止处理。 任何系统资源在收到设置的错误位后都必须采取行动来纠正故障。
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公开(公告)号：US06199144B1
公开(公告)日：2001-03-06
申请号：US09001336
申请日：1997-12-31
IPC分类号： G06F1200
CPC分类号： G06F12/0833
摘要： A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.
摘要翻译： 一种用于将数据从计算机系统中的第一存储器位置传送到第二存储器位置的方法和装置。 执行加载指令，并且作为响应，在单个总线事务期间，数据从第一存储器位置传送到第二存储器位置。 在相同的总线事务期间，如果加载指令指示这样做，则请求使存储在第三存储器位置的数据的副本无效。
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公开(公告)号：US5784708A
公开(公告)日：1998-07-21
申请号：US647074
申请日：1996-05-08
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/206
摘要： A computing system includes a memory bus, an input/output bus, a main memory, and an input/output adapter. The memory bus provides information transfer. The input/output bus also provides information transfer. For example the input/output bus is an input/output bus onto which is connected input/output devices. The main memory is connected to the memory bus. The main memory includes a page directory. The page directory stores translations. Each translation in the page directory includes a portion of an address for data transferred over the input/output bus, for example, the page address portion of I/O bus address. Each translation in the page directory also is indexed by a portion of an address for a memory location within the main memory, for example, the page address portion of the address for the memory location. The input/output adapter is connected to the memory bus and the input/output bus. The input/output adapter includes an input/output translation look-aside buffer. The input/output translation look-aside buffer includes a portion of the translations stored in the page directory.
摘要翻译： 计算系统包括存储器总线，输入/输出总线，主存储器和输入/输出适配器。 内存总线提供信息传输。 输入/输出总线还提供信息传输。 例如，输入/输出总线是输入/输出总线，连接有输入/输出总线。 主存储器连接到存储器总线。 主内存包括一个页面目录。 页面目录存储翻译。 页面目录中的每个翻译包括通过输入/输出总线传送的数据的地址的一部分，例如I / O总线地址的页面地址部分。 页面目录中的每个翻译也由主存储器内的存储器位置的地址的一部分索引，例如存储器位置的地址的页面地址部分。 输入/输出适配器连接到存储器总线和输入/输出总线。 输入/输出适配器包括一个输入/输出转换后备缓冲器。 输入/输出转换后备缓冲器包括存储在页目录中的一部分翻译。
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37.发明授权Partial cache line write transactions in a computing system with a write back cache 失效在具有回写高速缓存的计算系统中部分高速缓存行写入事务
公开(公告)号：US5586297A
公开(公告)日：1996-12-17
申请号：US217588
申请日：1994-03-24
CPC分类号： G06F12/0835 , G06F12/0886
摘要： A computing system is presented which includes a memory, an input/output adapter and a processor. The processor includes a write back cache in which dirty data may be stored. When performing a coherent write from the input/output adapter to the memory, a block of data is written from the input/output adapter to a memory location within the memory. The block of data contains less data than a full cache line in the write back cache. The write back cache is searched to determine whether the write back cache contains data for the memory location. When the search determines that the write back cache contains data for the memory location a full cache line which contains the data for the memory location is purged.
摘要翻译： 提出了一种包括存储器，输入/输出适配器和处理器的计算系统。 处理器包括可以存储脏数据的回写高速缓存。 当从输入/输出适配器执行相干写入到存储器时，将一块数据从输入/输出适配器写入存储器中的存储器位置。 数据块中的数据量少于写回缓存中的完整高速缓存行数据。 搜索回写高速缓存以确定回写高速缓存是否包含存储器位置的数据。 当搜索确定回写高速缓存包含用于存储器位置的数据时，清除包含存储器位置的数据的完整高速缓存行。
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38.发明授权Computer with multiple processors having varying priorities for access to a multi-element memory 失效具有多个优先权的计算机，用于访问多元素存储器
公开(公告)号：US5133059A
公开(公告)日：1992-07-21
申请号：US639413
申请日：1991-01-10
CPC分类号： G06F12/084 , G06F13/18
摘要： A parallel processing computer is disclosed in which a plurality of memory elements (e.g., caches) are accessable by a plurality of processors, and in which a fixed access priority for the processors is varied periodically to reduce differences in processing times between the processors in applications where memory access conflicts occur. The variation in priority is done infrequently enough so as not to disturb the ability of the system to avoid memory access conflicts by falling into a "lockstep" condition, in which the fixed priority combined with a selected interleaving of the memory elements produces a memory access pattern that, for certain memory strides, produces no memory access conflicts.
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公开(公告)号：US4622630A
公开(公告)日：1986-11-11
申请号：US546514
申请日：1983-10-28
IPC分类号： G06F13/18 , G06F13/37 , G06F13/378 , G06F9/00
CPC分类号： G06F13/37 , G06F13/18 , G06F13/378
摘要： In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.
摘要翻译： 在使用公共总线用于多个系统组件中的地址和数据信息的通信的数据处理系统中，总线定时技术使用具有传输时间段的时钟信号，该时间周期包括要发生地址传送的多个子周期 在第一选择的子周期期间和在第二选择的子周期期间要传输的数据，其中在其间具有空闲子周期。 第一控制信号由数据接收或数据提供单元产生，以便在这种传输完成之前禁止对总线的访问，并且如果需要多于一个的话可以提供第二控制信号来锁定总线访问 转让期。 布置适当的优先级，用于所选择的系统组件之间的总线访问，无论公共总线系统是否具有用于单个端口存储器的单个总线或与双端口存储器一起使用的双总线。
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公开(公告)号：US09426083B2
公开(公告)日：2016-08-23
申请号：US12569824
申请日：2009-09-29
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： H04L12/801 , H04L12/931 , H04L12/939
CPC分类号： H04L47/39 , H04L49/505 , H04L49/555
摘要： A credit-based method for controlling data communications in a computer system between a sender and a receiver coupled by an ordered communication link is described herein. A request for a credit check is transmitted from the sender to the receiver via the ordered communication link. An initial number of credits are allocated to the sender in a credit counter. A snapshot counter is set to a value of the credit counter and us updated as returned credits are received. A number of reported credits are determined based on a credit check response message received from the receiver. The returned credits are ordered relative to the credit check response message. The number of credits is checked for consistency based on a number of the snapshot counter and the number of reported credits.
摘要翻译： 这里描述了一种用于控制计算机系统中的数据通信的方法，该系统在由有序通信链路耦合的发送器和接收器之间。 通过有序的通信链路，从发送方向接收方发送信用检查请求。 在信用计数器中向发送者分配初始数量的信用。 快照计数器被设置为信用计数器的值，并且当接收到返回信用时我们更新。 基于从接收器接收的信用检查响应消息来确定多个报告信用。 返回的信用额度相对于信用检查响应消息进行排序。 基于快照计数器的数量和报告的信用数量，检查信用数量的一致性。
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