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公开(公告)号：US20100119961A1
公开(公告)日：2010-05-13
申请号：US12613221
申请日：2009-11-05
申请人： Jun YE , Yu Cao , Hanying Feng
发明人： Jun YE , Yu Cao , Hanying Feng
CPC分类号： G06F17/50 , G03F1/144 , G03F1/36 , G03F1/68 , G03F7/70433 , G03F7/705 , G03F7/70516
摘要： A method of efficient optical and resist parameters calibration based on simulating imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and generating the simulated image utilizing the function, where the simulated image represents the imaging result of the target design for the lithographic process. Systems and methods for calibration of lithographic processes whereby a polynomial fit is calculated for a nominal configuration of the optical system and which can be used to estimate critical dimensions for other configurations.
摘要翻译： 一种基于模拟用于对具有多个特征进行成像的目标设计的光刻工艺的成像性能的有效的光学和抗蚀剂参数校准的方法。 该方法包括以下步骤：确定用于产生模拟图像的功能，其中该功能考虑到与光刻工艺相关联的工艺变化; 并利用该功能产生模拟图像，其中模拟图像表示用于光刻工艺的目标设计的成像结果。 用于校准光刻过程的系统和方法，由此针对光学系统的标称配置计算多项式拟合，并且其可以用于估计其他配置的关键尺寸。
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32.发明申请公开(公告)号：US20080301620A1
公开(公告)日：2008-12-04
申请号：US11757805
申请日：2007-06-04
申请人： Jun Ye , Yu Cao , Hanying Feng
发明人： Jun Ye , Yu Cao , Hanying Feng
CPC分类号： G03F1/36
摘要： Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine tune already-placed SRAFs. In another embodiment the SRAF guidance map is used directly to place SRAFs in a mask layout.
摘要翻译： 公开了创建有效的基于模型的子分辨率辅助特征（MB-SRAF）的方法。 创建SRAF指南图，其中每个设计目标边缘位置对于给定的场点投票，放置在该场点上的单像素SRAF是否将改善或降级过程窗口上的空中图像。 在一个实施例中，SRAF引导图用于确定SRAF放置规则和/或微调已经放置的SRAF。 在另一个实施例中，SRAF引导图被直接用于将SRAF放置在掩模布局中。
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公开(公告)号：US08589829B2
公开(公告)日：2013-11-19
申请号：US13736929
申请日：2013-01-08
申请人： Peng Liu , Yu Cao , Luoqi Chen , Jun Ye
发明人： Peng Liu , Yu Cao , Luoqi Chen , Jun Ye
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/144 , G03F1/36 , G03F7/705 , G06F17/5009
摘要： A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.
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公开(公告)号：US07117478B2
公开(公告)日：2006-10-03
申请号：US11037988
申请日：2005-01-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20050122500A1
公开(公告)日：2005-06-09
申请号：US11037988
申请日：2005-01-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20050097500A1
公开(公告)日：2005-05-05
申请号：US10981914
申请日：2004-11-04
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20110083113A1
公开(公告)日：2011-04-07
申请号：US12964697
申请日：2010-12-09
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的单独功能或所使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。 在这方面，在一个实施例中，本发明采用光刻仿真系统架构，包括特定于应用的硬件加速器，以及用于加速和促进掩模设计的验证，表征和/或检验的处理技术，例如RET设计 ，包括对整个光刻工艺进行详细的仿真和表征，以验证设计在最终的晶片图案上实现和/或提供期望的结果。 该系统包括：（1）通用目的型计算设备，用于执行在数据处理中具有分支和相互依赖性的基于案例的逻辑，以及（2）加速器子系统执行大部分计算密集型任务。
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公开(公告)号：US20050120327A1
公开(公告)日：2005-06-02
申请号：US11024121
申请日：2004-12-28
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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39.发明授权System and method for creating a focus-exposure model of a lithography process 有权用于创建光刻工艺的焦点曝光模型的系统和方法公开(公告)号：US07747978B2
公开(公告)日：2010-06-29
申请号：US11461994
申请日：2006-08-02
申请人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
发明人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
IPC分类号： G06F17/50
CPC分类号： G03F7/70641 , G03F7/705 , G03F7/70516 , G03F7/70625
摘要： A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.
摘要翻译： 公开了一种用于创建光刻工艺的聚焦曝光模型的系统和方法。 系统和方法利用参数变化的多个维度的校准数据，特别是在曝光 - 散焦过程窗口空间内。 该系统和方法提供了一套统一的模型参数值，可在标称工艺条件下提供更好的模拟精度和鲁棒性，以及能够在整个过程窗口区域内连续预测任何点的光刻性能，而无需 重新校准在不同的设置。 与现有技术的多模型校准相比，要进行的测量数量要少一些，聚焦曝光模型提供了更多的预测性和更健壮的模型参数值，可以在过程窗口中的任何位置使用。
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40.发明申请SYSTEM AND METHOD FOR CREATING A FOCUS-EXPOSURE MODEL OF A LITHOGRAPHY PROCESS 有权用于创建光刻过程的聚焦曝光模型的系统和方法公开(公告)号：US20070031745A1
公开(公告)日：2007-02-08
申请号：US11461994
申请日：2006-08-02
申请人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
发明人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
CPC分类号： G03F7/70641 , G03F7/705 , G03F7/70516 , G03F7/70625
摘要： A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.
摘要翻译： 公开了一种用于创建光刻工艺的聚焦曝光模型的系统和方法。 系统和方法利用参数变化的多个维度的校准数据，特别是在曝光 - 散焦过程窗口空间内。 该系统和方法提供了一套统一的模型参数值，可在标称工艺条件下提供更好的模拟精度和鲁棒性，以及能够在整个过程窗口区域内连续预测任何点的光刻性能，而无需 重新校准在不同的设置。 与现有技术的多模型校准相比，要进行的测量数量要少一些，聚焦曝光模型提供了更多的预测性和更健壮的模型参数值，可以在过程窗口中的任何位置使用。
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