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公开(公告)号：US11362800B2
公开(公告)日：2022-06-14
申请号：US16781910
申请日：2020-02-04
申请人： Kandou Labs SA
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
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公开(公告)号：US11349459B2
公开(公告)日：2022-05-31
申请号：US17210260
申请日：2021-03-23
申请人： Kandou Labs SA
摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
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33.发明授权公开(公告)号：US11038518B2
公开(公告)日：2021-06-15
申请号：US16897033
申请日：2020-06-09
申请人： Kandou Labs SA
摘要： Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
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公开(公告)号：US20210111931A1
公开(公告)日：2021-04-15
申请号：US17081562
申请日：2020-10-27
申请人： Kandou Labs SA
发明人： Ali Hormati , Armin Tajalli , Amin Shokrollahi
摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
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公开(公告)号：US20200321967A1
公开(公告)日：2020-10-08
申请号：US16909520
申请日：2020-06-23
申请人： Kandou Labs SA
发明人： Armin Tajalli , Ali Hormati
摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
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公开(公告)号：US20200321915A1
公开(公告)日：2020-10-08
申请号：US16843785
申请日：2020-04-08
申请人： Kandou Labs SA
IPC分类号： H03B5/24
摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
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公开(公告)号：US20200235963A1
公开(公告)日：2020-07-23
申请号：US16836551
申请日：2020-03-31
申请人： Kandou Labs SA
发明人： Ali Hormati , Armin Tajalli , Amin Shokrollahi
摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
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公开(公告)号：US09203402B1
公开(公告)日：2015-12-01
申请号：US14089577
申请日：2013-11-25
申请人： Kandou Labs SA
发明人： Armin Tajalli , Harm Cronie , Amin Shokrollahi
IPC分类号： H03M5/00 , H03K17/687 , H03M13/29 , G11B20/14 , H04L1/00 , H03F1/32 , H04B3/54 , H04B1/7156
CPC分类号： H03M5/14 , G11B20/1426 , H03F1/3247 , H03K17/6871 , H03M13/2957 , H04B1/7156 , H04B3/54 , H04L1/0003 , H04L1/0048 , H04L1/0053 , H04L1/0057 , H04L1/0059
摘要： Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.
摘要翻译： 与平衡代码匹配的电路可以以噪声弹性和功率有效的方式恢复发送的信息。 用于处理平衡码的电路组件可以包括以下中的一个或多个：表示平衡码的信号的匹配放大，表示平衡码的信号的匹配均衡和/或滤波，对表示平衡码的信令进行匹配的非线性滤波 以检测特定符号的存在和表示平衡码的信号的匹配锁存。 这样的匹配电路和电路组件可以至少部分地通过将合适的公共电路节点和/或单个能量源并入到电路拓扑中来实现。
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