公开(公告)号：US11693733B2

公开(公告)日：2023-07-04

申请号：US17154661

申请日：2021-01-21

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Yasuhiko Kurosawa

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  H03M13/2906

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

公开(公告)号：US11689219B1

公开(公告)日：2023-06-27

申请号：US17401215

申请日：2021-08-12

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/11 ,  H03M13/29

CPC classification number: H03M13/118 ,  H03M13/2909

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

公开(公告)号：US20220209791A1

公开(公告)日：2022-06-30

申请号：US17135722

申请日：2020-12-28

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Amir Nassie ,  Anat Rot ,  Ofir Kanter ,  Hanan Weingarten

IPC: H03M13/11

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

公开(公告)号：US12197283B2

公开(公告)日：2025-01-14

申请号：US18184862

申请日：2023-03-16

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner

IPC: G06F11/10

Abstract: Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.

公开(公告)号：US12189476B2

公开(公告)日：2025-01-07

申请号：US18325370

申请日：2023-05-30

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Yasuhiko Kurosawa

IPC: G06F11/10 ,  H03M13/29

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include generating the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

公开(公告)号：US12176924B2

公开(公告)日：2024-12-24

申请号：US18184916

申请日：2023-03-16

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Ofir Kanter ,  Hanan Weingarten ,  Assaf Sella ,  Nimrod Bregman ,  Yasuhiko Kurosawa

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/29

Abstract: Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.

公开(公告)号：US20240311236A1

公开(公告)日：2024-09-19

申请号：US18184862

申请日：2023-03-16

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner

IPC: G06F11/10

CPC classification number: G06F11/1068

Abstract: Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.

公开(公告)号：US12087362B2

公开(公告)日：2024-09-10

申请号：US17702359

申请日：2022-03-23

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Kenji Sakurada ,  Eyal Nitzan ,  Yasuhiko Kurosawa

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

公开(公告)号：US20230253985A1

公开(公告)日：2023-08-10

申请号：US17586290

申请日：2022-01-27

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Zion Nahisi ,  Ofir Kanter ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/11 ,  H03M13/15

CPC classification number: H03M13/1128 ,  H03M13/152 ,  H03M13/1108 ,  H03M13/1125

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

公开(公告)号：US11563450B1

公开(公告)日：2023-01-24

申请号：US16818969

申请日：2020-03-13

Applicant: KIOXIA Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Hanan Weingarten

IPC: H03M13/45 ,  H03M13/29 ,  H03M13/11 ,  G06F3/06

Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.