Bit error rate estimation and classification in NAND flash memory

    公开(公告)号:US12176044B1

    公开(公告)日:2024-12-24

    申请号:US18123232

    申请日:2023-03-17

    Abstract: A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

    Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation

    公开(公告)号:US12009840B2

    公开(公告)日:2024-06-11

    申请号:US17569007

    申请日:2022-01-05

    Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

    SYSTEMS AND METHODS OF DECODING ERROR CORRECTION CODE OF A MEMORY DEVICE WITH DYNAMIC BIT ERROR ESTIMATION

    公开(公告)号:US20230216526A1

    公开(公告)日:2023-07-06

    申请号:US17569007

    申请日:2022-01-05

    CPC classification number: H03M13/43 H03M13/1575 H03M13/015

    Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

    EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT INFORMATION

    公开(公告)号:US20250037784A1

    公开(公告)日:2025-01-30

    申请号:US18915022

    申请日:2024-10-14

    Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

    DYNAMIC INTERFERENCE COMPENSATION FOR SOFT DECODING IN MEMORY STORAGE DEVICES

    公开(公告)号:US20250006265A1

    公开(公告)日:2025-01-02

    申请号:US18828352

    申请日:2024-09-09

    Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

    EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT INFORMATION

    公开(公告)号:US20240312552A1

    公开(公告)日:2024-09-19

    申请号:US18185198

    申请日:2023-03-16

    CPC classification number: G11C29/52 G11C29/022 G11C29/024

    Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

    Deep neural network implementation for soft decoding of BCH code

    公开(公告)号:US12050514B1

    公开(公告)日:2024-07-30

    申请号:US18184872

    申请日:2023-03-16

    CPC classification number: G06F11/1068 H03M13/152

    Abstract: Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

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