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公开(公告)号：US12009840B2
公开(公告)日：2024-06-11
申请号：US17569007
申请日：2022-01-05
Applicant: Kioxia Corporation
Inventor： Ofir Kanter , Avi Steiner , Yasuhiko Kurosawa
CPC classification number: H03M13/3715 , H03M13/3707 , H03M13/015 , H03M13/1575 , H03M13/43
Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
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2.发明公开公开(公告)号：US20230216526A1
公开(公告)日：2023-07-06
申请号：US17569007
申请日：2022-01-05
Applicant: Kioxia Corporation
Inventor： Ofir Kanter , Avi Steiner , Yasuhiko Kurosawa
CPC classification number: H03M13/43 , H03M13/1575 , H03M13/015
Abstract: A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
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公开(公告)号：US20250037784A1
公开(公告)日：2025-01-30
申请号：US18915022
申请日：2024-10-14
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter , Yasuhiko Kurosawa
Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.
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公开(公告)号：US12119075B2
公开(公告)日：2024-10-15
申请号：US18185198
申请日：2023-03-16
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter , Yasuhiko Kurosawa
IPC: G06F11/10 , G06F11/07 , G06F11/30 , G06F13/16 , G06F13/28 , G11C29/02 , G11C29/52 , H03M13/11 , H03M13/15
CPC classification number: G11C29/52 , G11C29/022 , G11C29/024
Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.
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公开(公告)号：US20240312552A1
公开(公告)日：2024-09-19
申请号：US18185198
申请日：2023-03-16
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter , Yasuhiko Kurosawa
CPC classification number: G11C29/52 , G11C29/022 , G11C29/024
Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.
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Patent Agency Ranking
公开(公告)号：US12050514B1
公开(公告)日：2024-07-30
申请号：US18184872
申请日：2023-03-16
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter
CPC classification number: G06F11/1068 , H03M13/152
Abstract: Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.
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公开(公告)号：US11790984B1
公开(公告)日：2023-10-17
申请号：US17703199
申请日：2022-03-24
Applicant: Kioxia Corporation
Inventor： Nimrod Bregman , Ofir Kanter
IPC: G11C11/4099 , G11C11/4096 , G11C11/54 , G06F18/22 , G06F18/214
CPC classification number: G11C11/4099 , G06F18/214 , G06F18/22 , G11C11/4096 , G11C11/54
Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.
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公开(公告)号：US20230085730A1
公开(公告)日：2023-03-23
申请号：US18070056
申请日：2022-11-28
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Amir Nassie , Anat Rot , Ofir Kanter , Hanan Weingarten
Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
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公开(公告)号：US20250007537A1
公开(公告)日：2025-01-02
申请号：US18887114
申请日：2024-09-17
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Zion Nahisi , Ofir Kanter , Amir Nassie , Hanan Weingarten
Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
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公开(公告)号：US20240385928A1
公开(公告)日：2024-11-21
申请号：US18787270
申请日：2024-07-29
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter
Abstract: Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.
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