公开(公告)号：US06826681B2

公开(公告)日：2004-11-30

申请号：US09882285

申请日：2001-06-18

申请人： Kevin D. Kissell ,  Hartvig W. J. Ekner

发明人： Kevin D. Kissell ,  Hartvig W. J. Ekner

IPC分类号： G06F940

CPC分类号： G06F9/30043 ,  G06F8/441 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/4484 ,  G06F9/4486

摘要： A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

摘要翻译： 一种方法和装置提供用于保存和恢复处理器寄存器值并分配和重新分配堆栈存储器的装置。 保存指令的第一个字段对处理器的寄存器中的值是否保存为参数值或静态值进行编码。 保存指令的第二个字段编码在执行保存指令期间创建的堆栈帧的大小。 参数值保存在调用程序的堆栈帧中。 静态值保存在被调用程序的堆栈帧中。 恢复指令用于恢复静态值并释放堆栈帧。 可以使用包括单个指令集架构处理器或多指令集架构处理器的任何可编程器件来执行保存和恢复指令。

公开(公告)号：US06651156B1

公开(公告)日：2003-11-18

申请号：US09822783

申请日：2001-03-30

申请人： David A. Courtright ,  Lawrence H. Hudepohl ,  Kevin D. Kissell ,  G. Michael Uhler

发明人： David A. Courtright ,  Lawrence H. Hudepohl ,  Kevin D. Kissell ,  G. Michael Uhler

IPC分类号： G06F1210

CPC分类号： G06F12/1027

摘要： An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page. The extended memory attributes index field is a field that is also employed by a legacy memory management protocol to prescribe legacy properties. The plurality of extended attributes registers are initialized to states that correspond to the legacy properties so that the CPU is compatible with operating systems employing the legacy memory management protocol.

摘要翻译： 提供了一种装置和方法，其使得中央处理单元（CPU）能够扩展虚拟存储器的属性，超过CPU内的现有转换后备缓冲器能够存储的属性，同时保持与传统操作系统软件的兼容性。 该装置包括翻译后备缓冲器和扩展属性逻辑。 翻译后备缓冲器（TLB）存储多个TLB条目。 每个TLB条目具有扩展的内存属性索引字段。 扩展属性逻辑耦合到TLB。 扩展属性逻辑使用扩展存储器属性索引字段来访问TLB外部的多个扩展存储器属性寄存器中的一个。 扩展内存属性寄存器的内容规定了相应虚拟内存页面的特定扩展属性。 扩展内存属性索引字段是旧的内存管理协议也用于规定遗留属性的字段。 多个扩展属性寄存器被初始化为对应于传统属性的状态，使得CPU与使用传统存储器管理协议的操作系统兼容。

公开(公告)号：US08145884B2

公开(公告)日：2012-03-27

申请号：US12605201

申请日：2009-10-23

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3009 ,  G06F8/4442 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4881 ,  G06F9/54

摘要： A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

摘要翻译： 公开了一种用于在多线程微处理器上执行并占据单个指令发布槽的fork指令。 在父线程中执行的fork指令包括指定新线程和第二操作数的初始指令地址的第一操作数。 微处理器通过为新线程分配上下文来执行fork指令，将第一操作数复制到新线程上下文的程序计数器，将第二操作数复制到新线程上下文的寄存器，并调度新线程以执行。 如果没有新的线程上下文可用于分配，则微处理器向fork指令引发异常。 fork指令是高效的，因为它不会将父线程通用寄存器复制到新线程。 第二个操作数通常用作指向包含新线程的初始通用寄存器集值的内存中的数据结构的指针。

公开(公告)号：US07725689B2

公开(公告)日：2010-05-25

申请号：US11615960

申请日：2006-12-23

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/455 ,  G06F9/4812 ,  G06F9/4881 ,  Y02D10/24

摘要： A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a translation lookaside buffer (TLB), shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the TLB, and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

摘要翻译： 公开了一种包括多线程微处理器和多处理器操作系统（OS）的多处理系统。 微处理器包括多个线程上下文（TC），每个线程上下文具有程序计数器和用于执行线程的通用寄存器集。 微处理器还包括由多个TC共享的翻译后备缓冲器（TLB），而不是被复制用于多个TC中的每一个，并且仅被操作系统特权的线程而不是由用户特权的线程而被管理。 操作系统管理TLB，并且调度操作系统特权线程和多个TC上的用户特权线程的执行。

公开(公告)号：US07676660B2

公开(公告)日：2010-03-09

申请号：US11949603

申请日：2007-12-03

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3009 ,  G06F8/4442 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4881 ,  G06F9/54

摘要： A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input operand specifies one or more of the independently occurring events. The yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of the independently occurring events specified by the input operand has occurred. The program thread contains the yield instruction. The yield instruction further instructs the microprocessor core to return a value in the output operand indicating which of the independently occurring events occurred to cause the microprocessor core to resume issuing the instructions of the program thread.

摘要翻译： 微处理器核心包括指示是否已经发生相应的多个独立发生的事件的多个输入。 输入是非内存地址输入。 核心还包括其指令集架构中的产出指令，包括用户可见的输出操作数和显式输入操作数。 输入操作数指定一个或多个独立发生的事件。 产出指令指示微处理器核心暂停执行程序线程的执行指令，直到发生由输入操作数指定的至少一个独立发生的事件。 程序线程包含yield指令。 产出指令进一步指示微处理器核心返回输出操作数中的值，指示发生哪些独立发生的事件，以使微处理器核心恢复发出程序线程的指令。

公开(公告)号：US07620832B2

公开(公告)日：2009-11-17

申请号：US11257381

申请日：2005-10-24

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F21/81 ,  G06F21/75

摘要： An apparatus and method are provided that disassociates the power consumed by a processing system from the instructions that it executes. The apparatus includes a power predictor that predicts the power that will be consumed by the processing system during execution of particular instructions, and a subsystem inhibition control, that selectively turns on/off available subsystems within the processing system based on the power that is predicted to be consumed. By predicting the power that will be consumed during execution, and by selectively turning on/off particular subsystems, the total power consumed by the processing system can be made invariant, or random. In either case, a counterweight current can be added to the processing system, depending on which of the subsystems are available to be turned on/off, and which are turned on/off, to further disassociate the total power consumed by the processing system from the instructions it is executing.

摘要翻译： 提供了一种装置和方法，其将处理系统消耗的功率与其执行的指令分离。 该装置包括功率预测器，其预测在执行特定指令期间由处理系统消耗的功率，以及子系统禁止控制，其基于预测的功率选择性地打开/关闭处理系统内的可用子系统 被消耗 通过预测在执行期间将消耗的功率，并且通过选择性地打开/关闭特定子系统，处理系统消耗的总功率可以是不变的或随机的。 在任一种情况下，根据哪个子系统可以打开/关闭以及哪些是开启/关闭，可以将配重电流添加到处理系统，以进一步解除处理系统消耗的总功率与 它正在执行的指令。

公开(公告)号：US07594089B2

公开(公告)日：2009-09-22

申请号：US10955231

申请日：2004-09-30

申请人： Sanjay Vishin ,  Kevin D. Kissell ,  Darren M. Jones ,  Ryan C. Kinter

发明人： Sanjay Vishin ,  Kevin D. Kissell ,  Darren M. Jones ,  Ryan C. Kinter

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/1416 ,  G06F13/1642

摘要： A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selected by the arbiter to the gating memory; receiving the particular one access method associated with the particular one memory access method from the gating memory; and initiating a communication of the particular access method to the thread context associated with the particular one access instruction.

摘要翻译： 一种与具有门控存储器的多处理存储器系统一起使用的存储器接口，门控存储器将一个或多个存储器访问方法与存储器系统的多个存储器位置中的每一个相关联，其中门控存储器返回特定的一个存取方法 一个存储器位置响应于与特定一个存储器位置相关的存储器访问指令，该接口包括：存储用于特定存储器位置中的一个或多个的多个并发存储器访问指令的请求存储器，每个存储器访问指令从 相关联的独立线程上下文; 耦合到所述请求存储器的仲裁器，用于选择所述存储器访问指令中的特定一个以应用于所述门控存储器; 以及耦合到请求存储器和仲裁器的控制器，用于：将多个存储器访问指令存储在请求存储器中; 启动由仲裁器选择的特定一个存储器访问指令到门控存储器的应用; 从门控存储器接收与特定一个存储器访问方法相关联的特定一个访问方法; 以及发起特定访问方法与特定一个访问指令相关联的线程上下文的通信。

公开(公告)号：US07162621B2

公开(公告)日：2007-01-09

申请号：US09788682

申请日：2001-02-21

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30167 ,  G06F9/30181

摘要： An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In a example, the substitution logic sign-extends the at least one parameter to form an immediate value of the at least one expanded instruction in a manner specified by the at least one parameter selector. In another example, the substitution logic concatenates a first parameter and a second parameter of the virtual instruction to form an immediate value of the at least one expanded instruction in a manner specified by the at lest one parameter selector.

摘要翻译： 提供了可扩展的指令集架构。 在一个实施例中，微处理器包括存储器，虚拟指令扩展存储器和替代逻辑。 存储器存储包括索引和至少一个参数的至少一个虚拟指令。 虚拟指令扩展存储器包括至少一个指令模板和至少一个参数选择器。 替代逻辑形成至少一个扩展指令的序列。 在一个示例中，替代逻辑符号扩展至少一个参数，以由至少一个参数选择器指定的方式形成至少一个扩展指令的立即值。 在另一示例中，替代逻辑将虚拟指令的第一参数和第二参数连接起来，以由至少一个参数选择器指定的方式形成至少一个扩展指令的立即值。

公开(公告)号：US07017025B1

公开(公告)日：2006-03-21

申请号：US10186290

申请日：2002-06-27

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F12/1072 ,  Y10S707/99952

摘要： A method and apparatus within a computer processing environment is provided for proxy management of a plurality of memory management units connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, and proxy memory management units that translate virtual memory requests generated by each of the processing elements into physical address. If the virtual memory requests can be translated directly into a physical address, then the translation is performed and the memory request proceeds. However, if the virtual address cannot be translated into a physical address by the proxy memory management unit, then the unit alerts the proxy processor to perform a page table lookup to locate the physical address. The lookup updates the table in the proxy memory management unit and the memory access proceeds. Such lookup is transparent to the processing element that generated the memory access.

摘要翻译： 提供了一种计算机处理环境内的方法和装置，用于连接到统一存储器环境内的多个处理元件或核心的多个存储器管理单元的代理管理。 代理管理系统包括诸如RISC核心的代理处理器和将由每个处理元件生成的虚拟存储器请求转换成物理地址的代理存储器管理单元。 如果虚拟内存请求可以直接转换为物理地址，则执行转换并继续存储器请求。 然而，如果虚拟地址不能被代理存储器管理单元转换成物理地址，则该单元警告代理处理器执行页表查找以定位物理地址。 查找更新代理内存管理单元中的表，并进行内存访问。 这种查找对于生成内存访问的处理元素是透明的。

公开(公告)号：US07003630B1

公开(公告)日：2006-02-21

申请号：US10186330

申请日：2002-06-27

申请人： Kevin D. Kissell

发明人： Kevin D. Kissell

IPC分类号： G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/0815

摘要： A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, that monitors data transfers or ownership transfers between the processing elements. If the proxy processor determines that a data transfer in one of the proxy caches will affect the coherency within another proxy cache, the proxy processor executes proxy management instructions such as invalidate, flush, prefetch to the appropriate proxy caches to insure coherency between the proxy caches and the unified memory.

摘要翻译： 处理环境中的方法和装置被提供用于在统一存储器环境内连接到多个处理元件或核心的多个代理缓存的代理管理。 代理管理系统包括代理处理器，例如RISC核，其监视处理元件之间的数据传输或所有权转移。 如果代理处理器确定代理缓存之一中的数据传输将影响另一个代理缓存内的一致性，则代理处理器执行代理管理指令，例如无效，刷新，预取到适当的代理缓存以确保代理缓存之间的一致性 和统一记忆。