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71 条记录 (耗时 0.034 秒)

    Transmitting peer-to-peer transactions through a coherent interface
    36.
    发明授权
    Transmitting peer-to-peer transactions through a coherent interface 有权
    通过一致的界面传输对等交易

    公开(公告)号：US07210000B2

    公开(公告)日：2007-04-24

    申请号：US10832607

    申请日：2004-04-27

    申请人： Kenneth C. Creta ,  Robert G. Blankenship ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

    发明人： Kenneth C. Creta ,  Robert G. Blankenship ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

    IPC分类号： G06F13/00 ,  H03M13/00

    CPC分类号： G06F13/387 ,  G06F13/4265

    摘要： In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.

    摘要翻译： 在各种实施例中，本发明包括一种用于在相干系统的第一代理处从第一对等设备接收具有第一报头信息的交易的方法，将第二报头信息插入事务，并且使用 第二标题信息。 在一个这样的实施例中，第一报头可以是第一协议的报头，并且第二报头可以是用于通过相干系统隧道交易的不同协议。

    Memory read requests passing memory writes
    37.
    发明申请
    Memory read requests passing memory writes 审中-公开
    内存读取请求传递内存写入

    公开(公告)号：US20050289306A1

    公开(公告)日：2005-12-29

    申请号：US10879778

    申请日：2004-06-28

    申请人： Sridhar Muthrasanallur ,  Kenneth Creta

    发明人： Sridhar Muthrasanallur ,  Kenneth Creta

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1626

    摘要： Memory read and write requests are received. The read is received in accordance with a communication protocol that has a transaction ordering rule in which a memory read cannot pass a memory write. The memory read and write requests are forwarded to the first device in accordance with another communication protocol that has a transaction ordering rule in which a memory read may pass a memory write. The forwarded memory read request is allowed to pass the forwarded memory write request whenever a relaxed ordering flag in the received read request is asserted. Other embodiments are also described and claimed.

    摘要翻译： 接收到存储器读写请求。 根据具有事务排序规则的通信协议接收读取，其中存储器读取不能通过存储器写入。 存储器读和写请求根据具有事务排序规则的另一通信协议被转发到第一设备，其中存储器读取可以通过存储器写入。 只要断言所接收到的读取请求中的松弛的排序标志，转发的存储器读取请求被允许通过转发的存储器写入请求。 还描述和要求保护其他实施例。

    Apparatus and method to maximize buffer utilization in an I/O controller
    38.
    发明授权
    Apparatus and method to maximize buffer utilization in an I/O controller 有权
    使I / O控制器中缓冲区利用率最大化的装置和方法

    公开(公告)号：US09378173B2

    公开(公告)日：2016-06-28

    申请号：US12704470

    申请日：2010-02-11

    申请人： Mahesh U. Wagh ,  Wilfred W. Kwok ,  Sridhar Muthrasanallur

    发明人： Mahesh U. Wagh ,  Wilfred W. Kwok ,  Sridhar Muthrasanallur

    IPC分类号： G06F3/00 ,  G06F13/40 ,  H04L12/801 ,  H04L12/40

    CPC分类号： G06F13/4059 ,  H04L12/4013 ,  H04L47/10

    摘要： An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

    摘要翻译： 一种用于使用I / O控制器中包含的信用管理逻辑使I / O控制器中的缓冲器利用率最大化的装置和方法。 信用管理逻辑跟踪I / O控制器中可用的存储器信用数量，并与连接到I / O控制器的芯片组通信可用存储器信用量。 然后，芯片组可以向I / O控制器发送一定量的数据，该数量等于或小于通信的可用量的存储器信用以减少“重试”事件的发生。 通过比较I / O控制器中的每个缓冲器中的可用存储器并且指定I / O控制器的“可用”存储器量是相当于包含在I / O控制器中的存储器量的量 具有最少可用内存的缓冲区。 然后可以将这个“可用”量的I / O控制器存储器转换成存储器信用并传送到芯片组。

    Size-based interleaving in a packet-based link
    39.
    发明授权
    Size-based interleaving in a packet-based link 有权
    基于分组的链路中基于大小的交织

    公开(公告)号：US07461218B2

    公开(公告)日：2008-12-02

    申请号：US11171716

    申请日：2005-06-29

    申请人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

    发明人： Sridhar Muthrasanallur ,  Jeff Wilder ,  Chitra Natarajan

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F13/1668

    摘要： A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

    摘要翻译： 在来自设备的端口处接收到存储器读取请求，其中端口通过基于分组的链路连接到设备。 存储器读取请求基于存储器读请求中请求的数据量排入小请求队列或大请求队列。 存储器读取请求在小请求队列和基于交织粒度的大请求队列之间进行交织。