公开(公告)号：US07527982B1

公开(公告)日：2009-05-05

申请号：US09617138

申请日：2000-07-14

申请人： Osamu Arisumi

发明人： Osamu Arisumi

IPC分类号： H01L21/00

CPC分类号： H01L21/02197 ,  C04B35/491 ,  C04B2235/3227 ,  C04B2235/75 ,  C04B2235/768 ,  C23C14/088 ,  C23C14/5806 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02266 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55

摘要： In order to improve the characteristic of the PZT film (insulation film of capacitor) of the PZT capacitor, after forming the amorphous PZT film, the amorphous PZT film is crystallized from at least the upper surface of the amorphous PZT film to form the PZT crystal film by employing the process whose sequence is reverse to that of the conventional process. In this case, the amorphous PZT film, which contains excessive oxygen and formed on the upper surface of the amorphous PZT film, is used as a seed.

摘要翻译： 为了提高PZT电容器的PZT膜（电容器的绝缘膜）的特性，在形成非晶PZT膜之后，至少从非晶PZT膜的上表面结晶化非晶PZT膜，形成PZT晶体 通过采用与常规方法相反的方法的方法。 在这种情况下，使用含有过量氧而形成在非晶PZT膜的上表面上的无定形PZT膜作为种子。

公开(公告)号：US07407864B2

公开(公告)日：2008-08-05

申请号：US11175305

申请日：2005-07-07

申请人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

发明人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

IPC分类号： H01L21/76

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76224

摘要： Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底中形成元件隔离沟槽，在其上形成元件隔离沟槽的半导体衬底上涂覆聚硅氮烷二次酐溶液以形成聚硅氮烷过渡膜，所述聚硅氮烷过硼酸盐溶液包含二丁基醚 具有30ppm以下的丁醇浓度，溶解在二丁基醚中的聚硅氮烷二烷基化钠，在含有水蒸汽的气氛中使聚硅氮烷二次酐膜氧化，形成二氧化硅膜，选择性地除去二氧化硅膜离开硅 元件隔离沟中的二氧化硅膜形成元件隔离绝缘膜。

公开(公告)号：US20060205165A1

公开(公告)日：2006-09-14

申请号：US11175305

申请日：2005-07-07

申请人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

发明人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

IPC分类号： H01L21/76

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76224

摘要： Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底中形成元件隔离沟槽，在其上形成元件隔离沟槽的半导体衬底上涂覆聚硅氮烷二次酐溶液以形成聚硅氮烷过渡膜，所述聚硅氮烷过硼酸盐溶液包含二丁基醚 具有30ppm以下的丁醇浓度，溶解在二丁基醚中的聚硅氮烷二烷基化钠，在含有水蒸汽的气氛中使聚硅氮烷二次酐膜氧化，形成二氧化硅膜，选择性地除去二氧化硅膜离开硅 元件隔离沟中的二氧化硅膜形成元件隔离绝缘膜。

公开(公告)号：US5886385A

公开(公告)日：1999-03-23

申请号：US914752

申请日：1997-08-20

申请人： Osamu Arisumi ,  Akira Nishiyama ,  Makoto Yoshimi

发明人： Osamu Arisumi ,  Akira Nishiyama ,  Makoto Yoshimi

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/45 ,  H01L29/786 ,  H01L27/01 ,  H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78618

摘要： A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.

摘要翻译： 半导体器件包括：具有第一导电性的第一半导体层6，其形成在具有绝缘材料4的表面的基板上; 源极区域16a和漏极区域16b，其形成在第一半导体层上以彼此分离并且具有不同于第一导电性的第二导电性; 形成在源极区域和漏极区域之间的第一半导体层上的沟道区域6; 形成在形成在栅极侧的绝缘材料的栅极侧壁14的沟道区域上的栅电极10; 以及在至少源极区上形成具有第一导电性的第二半导体层18。 该半导体装置能够以简单的结构有效地抑制浮体效应。

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。