公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5675176A

公开(公告)日：1997-10-07

申请号：US530721

申请日：1995-09-15

申请人： Yukihiro Ushiku ,  Atsushi Yagishita ,  Satoshi Inaba ,  Minoru Takahashi ,  Masanori Numano ,  Yoshiki Hayashi ,  Yoshiaki Matsushita ,  Yasunori Okayama ,  Hiroyasu Kubota ,  Norihiko Tsuchiya

发明人： Yukihiro Ushiku ,  Atsushi Yagishita ,  Satoshi Inaba ,  Minoru Takahashi ,  Masanori Numano ,  Yoshiki Hayashi ,  Yoshiaki Matsushita ,  Yasunori Okayama ,  Hiroyasu Kubota ,  Norihiko Tsuchiya

IPC分类号： H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L29/30

CPC分类号： H01L27/0921 ,  H01L27/10808 ,  H01L29/1079

摘要： A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.

摘要翻译： 半导体器件具有具有凹槽的半导体衬底和形成在半导体衬底的表面区域中的半导体元件。 具有与半导体基板不同的热膨胀系数的物质嵌入到槽的至少一部分中，从半导体衬底中的槽的底部附近的区域产生晶体缺陷，从而减轻其他区域中的应力和应变 使得这些区域不会在表面区域的半导体元件的电路操作所需的区域中产生晶体缺陷。

公开(公告)号：US5739575A

公开(公告)日：1998-04-14

申请号：US705647

申请日：1996-08-30

申请人： Masanori Numano ,  Norihiko Tsuchiya ,  Hiroyasu Kubota ,  Yoshiaki Matsushita ,  Yoshiki Hayashi ,  Yukihiro Ushiku ,  Atsushi Yagishita ,  Satoshi Inaba ,  Yasunori Okayama ,  Minoru Takahashi

发明人： Masanori Numano ,  Norihiko Tsuchiya ,  Hiroyasu Kubota ,  Yoshiaki Matsushita ,  Yoshiki Hayashi ,  Yukihiro Ushiku ,  Atsushi Yagishita ,  Satoshi Inaba ,  Yasunori Okayama ,  Minoru Takahashi

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/322 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L21/76237 ,  H01L21/74

摘要： Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.

摘要翻译： 具有亚微米级精细图案或精细图案的LSI的元件隔离技术。 在埋设绝缘材料（电介质）层的下面，远离用于元件隔离的方式形成掺杂高浓度杂质的高应变区。 由于这种埋置的电介质元件隔离（BDEI）结构，由于高应变层存在于掩埋电介质层的正下方，所以由于半导体层与埋入层之间的热膨胀系数的差异引起的应变引起的掩埋电介质层附近产生的晶体缺陷 电介质层向高应变层移动。 因此，晶体缺陷不会到达形成有源元件的有源区域，从而有利地减少了形成在有源层中的p-n结中的泄漏电流。

公开(公告)号：US5116780A

公开(公告)日：1992-05-26

申请号：US596732

申请日：1990-10-16

申请人： Shuichi Samata ,  Yoshiaki Matsushita

发明人： Shuichi Samata ,  Yoshiaki Matsushita

IPC分类号： H01L21/283 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/41 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/456

摘要： A multi-layered insulation film of non-doped CVD SiO.sub.2 (silicon dioxide) film and BPSG (boro-phospho-silicate glass) film is formed on a silicon substrate. Films have a contact hole exposing impurity diffused region formed in silicon substrate. A semiconductor layer is formed in the contact hole. An Al (aluminum) film is formed on the semiconductor layer. The semiconductor layer contacts the BPSG film so that the contact resistance between the semiconductor layer and the Al (aluminum) film can be reduced, and a variation of the contact resistance between respective semiconductor devices can also be reduced.

摘要翻译： 在硅衬底上形成非掺杂CVD SiO 2（二氧化硅）膜和BPSG（硼磷硅酸盐玻璃）膜的多层绝缘膜。 膜具有暴露在硅衬底中形成的杂质扩散区的接触孔。 在接触孔中形成半导体层。 在半导体层上形成Al（铝）膜。 半导体层与BPSG膜接触，能够降低半导体层与Al（铝）膜之间的接触电阻，能够降低各半导体器件之间的接触电阻的变化。

公开(公告)号：US5004702A

公开(公告)日：1991-04-02

申请号：US338794

申请日：1989-04-17

申请人： Shuichi Samata ,  Yoshiaki Matsushita

发明人： Shuichi Samata ,  Yoshiaki Matsushita

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/8238

CPC分类号： H01L21/28525 ,  H01L21/2257 ,  H01L21/823814

摘要： A semiconductor substrate having a surface region of P type and a surface region of N type is formed, then an insulating membrane is formed on the semiconductor substrate. The first contact hole which is formed in said region of P type and the second contact hole which is connected to said region of N type are formed by the same process as that for said insulating membrane. Non-doped silicon layer is grown in said first and second contact holes by the same selective growth process, in a single reactive furnace. A diffusion source layer containing impurities of P type is formed on said first contact hole and a diffusion source layer containing impurities of N type on said second contact hole. Impurities are diffused from said diffusion layers to said silicon layers, and said diffusion source layer is then removed. A metal wire layer is formed by connecting it to said silicon layer.

摘要翻译： 形成具有P型表面区域和N型表面区域的半导体衬底，然后在半导体衬底上形成绝缘膜。 在所述P型区域中形成的第一接触孔和与所述N型区域连接的第二接触孔通过与所述绝缘膜相同的工艺形成。 在单个反应炉中，非掺杂硅层通过相同的选择性生长工艺在所述第一和第二接触孔中生长。 在所述第一接触孔上形成含有P型杂质的扩散源层和在所述第二接触孔上含有N型杂质的扩散源层。 杂质从所述扩散层扩散到所述硅层，然后去除所述扩散源层。 通过将金属线层连接到所述硅层而形成金属线层。

公开(公告)号：US20080192345A1

公开(公告)日：2008-08-14

申请号：US11885685

申请日：2006-03-09

申请人： Noriaki Mochizuki ,  Kenichiro Yoshioka ,  Kouichi Tanaka ,  Yoshiaki Matsushita

发明人： Noriaki Mochizuki ,  Kenichiro Yoshioka ,  Kouichi Tanaka ,  Yoshiaki Matsushita

IPC分类号： G02B5/30 ,  B29D11/00 ,  G02F1/1335

CPC分类号： G02B5/3033 ,  B29C55/026 ,  B29C55/04 ,  B29K2029/04 ,  B29K2995/0034 ,  G02F1/133528 ,  Y10T428/1041

摘要： The present invention relates to a polarizing film obtained by stretching a polyvinyl alcohol resin film containing iodine, an iodide a cross-linking agent and/or waterproofing agent and then treating the film with a solution containing 0.0001 to 5.0 wt % of inorganic acid except for boric acid or a salt thereof and/or organic acid and having a pH of preferably 2≦pH≦5, more preferably 2.2≦pH≦5. Said polarizing film is excellent in wet heat durability and shows less decrease in polarization characteristics in wet heat test and said polarizing film obtained in a further preferable embodiment is also excellent in dry heat durability.

摘要翻译： 本发明涉及通过拉伸含碘的聚乙烯醇树脂膜，碘化物，交联剂和/或防水剂获得的偏振膜，然后用含有0.0001至5.0重量％的无机酸的溶液处理该膜，除了 硼酸或其盐和/或有机酸，并且pH优选为2 <= pH <= 5，更优选2.2 <= pH <= 5。 所述偏振膜的湿热耐久性优异，在湿热试验中偏振特性的降低较少，在另一优选实施方式中所获得的偏光膜的干热耐久性也优异。

公开(公告)号：US5994756A

公开(公告)日：1999-11-30

申请号：US751438

申请日：1996-11-20

申请人： Kaori Umezawa ,  Norihiko Tsuchiya ,  Yoshiaki Matsushita ,  Hiroyuki Kamijou ,  Atsushi Yagishita ,  Tsunehiro Kita

发明人： Kaori Umezawa ,  Norihiko Tsuchiya ,  Yoshiaki Matsushita ,  Hiroyuki Kamijou ,  Atsushi Yagishita ,  Tsunehiro Kita

IPC分类号： H01L21/762 ,  H01L27/04 ,  H01L23/58

CPC分类号： H01L21/76232 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283

摘要： A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide films using organic silicon source as material are buried in the grooves as buried oxide films. The present invention is characterized in that the buried oxide films are annealed at a predetermined temperature within the range of 1100 to 1350.degree. C. before or after planarization of the semiconductor substrate such that ring structures of more than 5-fold ring and ring structures of less than 4-fold ring are formed at predetermined rates in the buried oxide films. The above annealing allows stress of the oxide film buried in the grooves to be relaxed. Hence, the generation of dislocation is suppressed.

摘要翻译： 提供具有浅沟槽隔离（STI）结构的半导体衬底及其制造方法，即，在半导体衬底的预定位置选择性地形成沟槽并且使用有机硅源作为材料的氧化物膜的隔离衬底 埋在凹槽中作为掩埋氧化膜。 本发明的特征在于，在半导体衬底的平坦化之前或之后，在1100〜1350℃的范围内的预定温度下对所述埋入氧化物膜进行退火，使得所述半导体衬底的环结构超过5倍， 在掩埋氧化膜中以预定的速率形成小于4倍的环。 通过上述退火，能够缓和埋入槽内的氧化膜的应力。 因此，错位的产生被抑制。

公开(公告)号：US5246500A

公开(公告)日：1993-09-21

申请号：US937743

申请日：1992-09-01

申请人： Shuichi Samata ,  Yoshiaki Matsushita

发明人： Shuichi Samata ,  Yoshiaki Matsushita

IPC分类号： C30B25/10 ,  C23C16/455 ,  C30B25/14 ,  H01L21/00 ,  H01L21/205

CPC分类号： H01L21/67115 ,  C23C16/455 ,  C30B25/14

摘要： A vapor phase growth apparatus is disclosed, which comprises a boat accommodating therein a plurality of semiconductor substrates, an inner tube surrounding the boat, an outer tube disposed outside the inner tube, a heater disposed outside the outer tube, a reaction gas injection nozzle disposed inside the inner tube and operating to eject a reaction gas against the semiconductor substrates, and a hydrogen halide gas injection nozzle disposed between the inner tube and the outer tube and operating to inject the hydrogen halide gas, wherein exhaust openings for exhausting the reaction gas are formed through a wall of the inner tube, thereby suppressing deposition of a reactant on an outer surface of the inner tube and an inner surface of the outer tube. The reaction gas injected from the reaction gas injection nozzle flows in the portion formed between the inner tube and the outer tube along with in the inner tube. Since the portion between the inner tube and the outer tube is heated by the heater disposed outside the outer tube, a reactant tends to be deposited on the outer surface of the inner tube and the inner surface of the outer tube. By injecting the hydrogen halide gas from the hydrogen halide gas injection nozzle to the portion formed between the inner tube and the outer tube, the deposition of the reactant can be suppressed.

摘要翻译： 公开了一种气相生长装置，其包括容纳多个半导体衬底的舟皿，围绕舟皿的内管，设置在内管外部的外管，设置在外管外部的加热器，设置在反应气体注入喷嘴 在内管内部并且操作以将反应气体喷射到半导体基板上;以及卤化氢气体注入喷嘴，其设置在内管和外管之间并且操作以喷射卤化氢气体，其中用于排出反应气体的排气口为 通过内管的壁形成，从而抑制反应物沉积在内管的外表面和外管的内表面上。 从反应气体喷射喷嘴喷射的反应气体与内管一起流入形成在内管和外管之间的部分。 由于内管和外管之间的部分被设置在外管外部的加热器加热，反应物倾向于沉积在内管的外表面和外管的内表面上。 通过将卤化氢气体从卤化氢气体注入喷嘴注入到形成在内管和外管之间的部分，可以抑制反应物的沉积。

公开(公告)号：US5148457A

公开(公告)日：1992-09-15

申请号：US719706

申请日：1991-06-27

申请人： Atsuko Kubota ,  Norihiko Tsuchiya ,  Shuichi Samata ,  Yoshiaki Matsushita ,  Mokuji Kageyama

发明人： Atsuko Kubota ,  Norihiko Tsuchiya ,  Shuichi Samata ,  Yoshiaki Matsushita ,  Mokuji Kageyama

IPC分类号： G01N23/223

CPC分类号： G01N23/223 ,  G01N2223/076

摘要： A system for analyzing a metal impurity at the surface of a single crystal semiconductor comprising: an incident device for allowing X-ray to be incident, at an incident angle less than a total reflection angle, onto the surface of a wafer in the form of a thin plate comprised of a single crystal semiconductor (e.g., silicon); a wafer fixing/positioning stage wherein when it is assumed that the wafer surface is partitioned by a lattice having an interval d, and that the wavelength of the X-ray from the incident device is .lambda., an angle that the X-ray and the wafer surface form is .theta., and an arbitrary integer is n, the stage is adapted to fix the crystal orientation of the wafer so as to satisfy the condition of "2d sin .theta..noteq.n.lambda.", and to allow sample points to which X-ray is incident to be subjected to positioning by a horizontal movement; and analyzing device for measuring a light quantity of a fluorescent X-ray generated as the result of the fact that the incident X-ray excites atoms at the wafer surface to analyze a quantity of the metal impurity attached on the wafer surface under the condition that the Bragg reflection causing measurement noises does not take place.

公开(公告)号：US4894206A

公开(公告)日：1990-01-16

申请号：US91947

申请日：1987-09-01

申请人： Youji Yamashita ,  Masakatu Kojima ,  Yoshiaki Matsushita ,  Masanobu Ogino

发明人： Youji Yamashita ,  Masakatu Kojima ,  Yoshiaki Matsushita ,  Masanobu Ogino

IPC分类号： C30B15/12 ,  H01L21/18

CPC分类号： C30B15/12 ,  Y10S117/90 ,  Y10T117/1052

摘要： The present invention discloses a crystal pulling apparatus having a double-crucible structure, wherein an inner crucible is located in an outer crucible. An end of a pipe-like passage is located in a through hole formed in a side wall of an inner crucible located in an outer crucible, and a melt is supplied from the outer crucible to the inner crucible through the pipe-like passage, during crystal pulling. During melting or neckdown, prior to crystal pulling, diffusion of an impurity between the melts in the outer crucible and the inner crucible, and exchange of the melts between the outer crucible and the inner crucible are prevented by the pipe-like passage.

摘要翻译： 本发明公开了一种具有双坩埚结构的晶体拉制装置，其中内坩埚位于外坩埚中。 管状通道的端部位于形成在位于外坩埚内坩埚的侧壁中的通孔中，熔融物通过管状通道从外坩埚供应到内坩埚中 水晶拉。 在熔融或颈缩期间，在晶体拉伸之前，通过管状通道来防止杂质在外坩埚和内坩埚之间的熔体的扩散以及外坩埚和内坩埚之间的熔体的交换。