公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5629539A

公开(公告)日：1997-05-13

申请号：US400887

申请日：1995-03-08

申请人： Masami Aoki ,  Tohru Ozaki ,  Takashi Yamada ,  Hitomi Kawaguchiya

发明人： Masami Aoki ,  Tohru Ozaki ,  Takashi Yamada ,  Hitomi Kawaguchiya

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L29/94

摘要： A semiconductor memory device comprises a semiconductor substrate, a plurality of memory cells including a plurality of MOS transistors, each having a source, a drain and a gate, and a plurality of capacitors formed on the semiconductor substrate in a matrix manner, an interlayer insulating film formed on the memory cells and having a plurality of openings selectively formed, a plurality of plug electrodes formed in the openings of the interlayer insulating film, a plurality of bit lines, each bit line being connected to one of the source and the drain of each of the MOS transistors through a corresponding one of the plug electrodes, and a plurality word lines, each word line being the gate of each of the MOS transistors. The capacitors each comprise a storage node electrode having a cylindrical portion layered on another one of the source and the drain of each of the MOS transistors, a capacitor dielectric film formed on the storage node electrode, and a plate electrode formed to be opposed to at least the storage node electrode interposing the capacitor dielectric film therebetween. The bit lines are formed on the interlayer insulating film and connected to the upper surface of the plug electrode. The plug electrode has a pad electrode comprised of a lower side conductive member formed with a same layer as the storage node electrode and a cylindrical side wall conductive member, and an upper side conductive member formed on the pad electrode.

摘要翻译： 半导体存储器件包括半导体衬底，包括多个MOS晶体管的多个存储单元，每个MOS晶体管具有源极，漏极和栅极以及以矩阵方式形成在半导体衬底上的多个电容器，层间绝缘 形成在存储单元上并具有选择性地形成的多个开口的多个插塞电极，形成在层间绝缘膜的开口中的多个插塞电极，多个位线，每个位线连接到源极和漏极之一 每个MOS晶体管通过相应的一个插头电极和多个字线，每个字线是每个MOS晶体管的栅极。 电容器各自包括存储节点电极，其具有层叠在每个MOS晶体管的源极和漏极的另一个上的圆柱形部分，形成在存储节点电极上的电容器电介质膜和形成为与 存储节点电极至少插入电容器电介质膜之间。 位线形成在层间绝缘膜上并连接到插塞电极的上表面。 插头电极具有由形成有与蓄电节点电极相同层的下侧导电部件和圆筒状侧壁导电部件构成的焊盘电极，以及形成在焊盘电极上的上侧导电部件。

公开(公告)号：US5578847A

公开(公告)日：1996-11-26

申请号：US402570

申请日：1995-03-13

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

摘要翻译： 设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置 每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

公开(公告)号：US5747844A

公开(公告)日：1998-05-05

申请号：US736279

申请日：1996-10-24

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

公开(公告)号：US6078073A

公开(公告)日：2000-06-20

申请号：US878208

申请日：1997-06-18

申请人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

发明人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10844 ,  H01L21/76897 ,  H01L27/10873

摘要： A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

摘要翻译： 在形成在半导体衬底上的栅绝缘膜上形成具有层叠在其上部的第一绝缘膜的栅电极。 在栅电极的侧壁上形成侧壁，并且形成绝缘膜以覆盖栅电极和侧壁。 通过绝缘膜进行离子注入，从而在半导体衬底上形成扩散层。 形成层间电介质膜，然后选择性地蚀刻层间电介质膜和绝缘膜，从而以与栅电极自对准的方式形成露出栅极绝缘膜的开口部。 然后，去除开口部的底部的栅极绝缘膜，使得露出半导体基板的表面。 然后，形成与半导体基板的露出面连接的布线层。

公开(公告)号：US5736760A

公开(公告)日：1998-04-07

申请号：US632321

申请日：1996-04-15

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

公开(公告)号：US5508541A

公开(公告)日：1996-04-16

申请号：US124300

申请日：1993-09-20

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

摘要翻译： MOS随机存取存储器件包括其中形成有沟槽的半导体衬底和衬底上的存储器单元的阵列。 每个存储单元包括1位数据存储电容器和转移栅极MOS晶体管。 电容器包括埋在沟槽中的绝缘层，其用作存储节点。 岛状半导体层至少部分地覆盖基板上的存储节点层，并且与其耦合。 晶体管具有源极和漏极，在衬底中限定其间的沟道区域，以及覆盖沟道区域的绝缘栅极。 源极和漏极中的一个直接耦合到岛状层，而另一个与与其相关联的相应数据传输线（位线）接触。

公开(公告)号：US6043528A

公开(公告)日：2000-03-28

申请号：US806247

申请日：1997-02-21

申请人： Masami Aoki ,  Takeshi Hamamoto

发明人： Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  Y10S257/908

摘要： A semiconductor memory device comprises a MOS-type transistor formed on a semiconductor substrate, a capacitor formed in the interior of an opening portion formed in the semiconductor substrate to be adjacent to the MOS-type transistor, the capacitor having a capacitor insulating film formed of a high dielectric film, and a line layer for connecting respective gate electrodes of the MOS-type transistor separated to be island-shaped to prevent from being presented on a region where the opening portion is formed, the line layer formed of a conductive layer different from the gate electrodes in its level.

摘要翻译： 一种半导体存储器件，包括形成在半导体衬底上的MOS型晶体管，形成在与半导体衬底中形成的与MOS型晶体管相邻的开口部内部的电容器，该电容器具有由 高电介质膜和用于连接分离为岛状的MOS型晶体管的各个栅电极的线层，以防止形成在开口部分的区域上，由不同的导电层形成的线层 从门电极的电平。

公开(公告)号：US06294422B1

公开(公告)日：2001-09-25

申请号：US09468319

申请日：1999-12-21

申请人： Kazumasa Sunouchi ,  Masami Aoki

发明人： Kazumasa Sunouchi ,  Masami Aoki

IPC分类号： H01L218242

CPC分类号： H01L27/10852

摘要： In a stack type memory cell of 8F2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

摘要翻译： 在8F2的堆叠型存储单元中，形成用于将位线连接到两个字线WL之间的区域中的有源区的源极/漏极扩散层的位线插头电极，从源极/漏极扩散层平行延伸到字线 并且形成为比最小元件隔离宽度F长并且小于最小元件隔离宽度F的三倍。因此，可以实现使用堆叠型存储单元并且其积分密度可以容易地增强的DRAM。

公开(公告)号：US6025623A

公开(公告)日：2000-02-15

申请号：US927901

申请日：1997-09-11

申请人： Kazumasa Sunouchi ,  Masami Aoki

发明人： Kazumasa Sunouchi ,  Masami Aoki

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10852

摘要： In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

摘要翻译： 在8F2的堆叠型存储单元中，形成用于将位线连接到两个字线WL之间的区域中的有源区的源极/漏极扩散层的位线插头电极，从源极/漏极扩散层平行延伸到字线 并且形成为比最小元件隔离宽度F长并且小于最小元件隔离宽度F的三倍。因此，可以实现使用堆叠型存储单元并且其积分密度可以容易地增强的DRAM。