公开(公告)号：US08924619B2

公开(公告)日：2014-12-30

申请号：US13864494

申请日：2013-04-17

Applicant: LSI Corporation

Inventor： Earl T. Cohen ,  Mark vonGnechten

IPC: G06F13/16 ,  G06F5/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F15/173

Abstract: A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs . Each of the processors is associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via respective hardware unit input and output communication FIFOs. Each of the processors is enabled to send messages to others of the processors via respective processor output communication FIFOs. The respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input communication FIFOs.

Abstract translation: 系统包括多个处理器，消息结构和多个硬件单元。 多个处理器中的每一个包括多个通信FIFO，并且具有包括至少一个指令的指令集，以通过多个通信FIFO中的至少一个发送消息。 消息结构通过多个通信FIFO中的至少一些来耦合处理器。 每个处理器与相应的一个或多个硬件单元相关联，并经由相应的硬件单元输入和输出通信FIFO耦合到每个相关联的硬件单元。 每个处理器都能够通过相应的处理器输出通信FIFO将消息发送到处理器的其他处理器。 与每个处理器相关联的各个硬件单元能够经由相应的硬件单元输入通信FIFO向相关联的处理器发送消息。

公开(公告)号：US20140258769A1

公开(公告)日：2014-09-11

申请号：US13788303

申请日：2013-03-07

Applicant: LSI CORPORATION

Inventor： Leonid Baryudin ,  Alex G. Tang ,  Earl T. Cohen

IPC: G06F12/02 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F11/0793 ,  G06F11/1008 ,  G06F12/02 ,  G06F2211/109 ,  G06F2212/7205 ,  G11C16/3418 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.

Abstract translation: 一种装置包括非易失性存储器和控制器。 非易失性存储器包括多个R块。 控制器耦合到非易失性存储器。 控制器被配置为（i）使用R块作为分配单元来写入数据，以及（ii）选择性地在R块中的整个R块或小于全部R块中的一部分执行再循环操作 块。

公开(公告)号：US08791843B2

公开(公告)日：2014-07-29

申请号：US13651627

申请日：2012-10-15

Applicant: LSI Corporation

Inventor： Earl T. Cohen

IPC: H03M7/34 ,  H03M7/38

CPC classification number: H03M7/3084 ,  H03M7/3079

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a compressed representation of an input sequence of characters and (ii) statistics regarding one or more types of information in the compressed representation of the input sequence of characters. The second circuit may be configured to generate a compressed bitstream representation of the input sequence of characters in response to the compressed representation of the input sequence of characters and one or more of the statistics regarding the one or more types of information in the compressed representation of the input sequence of characters. The bitstream values encoding the one or more types of information are generally determined based upon a frequency of occurrence of the one or more types of information in the compressed representation of the input sequence of characters.

Abstract translation: 一种装置包括第一电路和第二电路。 第一电路可以被配置为产生（i）输入字符序列的压缩表示，以及（ii）关于输入字符序列的压缩表示中的一种或多种类型的信息的统计。 第二电路可以被配置为响应于输入的字符序列的压缩表示来产生输入的字符序列的压缩比特流表示，以及关于压缩表示中的一个或多个类型的信息的一个或多个统计信息 字符的输入序列。 编码一种或多种类型的信息的比特流值通常基于输入字符序列的压缩表示中的一种或多种类型的信息的出现频率来确定。

公开(公告)号：US20140136883A1

公开(公告)日：2014-05-15

申请号：US13677938

申请日：2012-11-15

Applicant: LSI CORPORATION

Inventor： Earl T. Cohen

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G11C16/3422 ,  G11C16/349

Abstract: An apparatus comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) accumulate a read disturb count for a first region of the non-volatile memory, (ii) accumulate error statistics for a second region of the non-volatile memory, (iii) determine, based upon both the read disturb count and the error statistics, whether the first region has reached a read disturb limit, and (iv) in response to determining that the first region has reached the read disturb limit, relocate at least some data of the first region.

Abstract translation: 一种包括非易失性存储器和控制器的装置。 控制器耦合到非易失性存储器并且被配置为（i）累积用于非易失性存储器的第一区域的读取干扰计数，（ii）累积非易失性存储器的第二区域的误差统计量（ iii）基于读取干扰计数和误差统计确定第一区域是否已经达到读取干扰极限，以及（iv）响应于确定第一区域已经达到读取干扰极限，重新定位至少一些 第一区域的数据。

公开(公告)号：US20150178149A1

公开(公告)日：2015-06-25

申请号：US14173108

申请日：2014-02-05

Applicant: LSI Corporation

Inventor： Yu Cai ,  Ning Chen ,  Yunxiang Wu ,  Erich F. Haratsch ,  Earl T. Cohen ,  Timothy L. Canepa

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072

Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

Abstract translation: 一种装置包括存储器和控制器。 存储器包括多个存储器件。 每个存储器设备具有多个页面类型。 基于错误率变化对多个页面类型进行分类。 控制器可以被配置为将用户数据和纠错数据写入存储器。 用户数据和纠错数据被组织为超级页面。 超级页面包括多个子页面。 多个子页面被跨越多个存储器件写入，使得使用多个页面类型中的多个页面类型存储多个子页面。

公开(公告)号：US20150149855A1

公开(公告)日：2015-05-28

申请号：US14100280

申请日：2013-12-09

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Earl T. Cohen

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.

Abstract translation: 公开了一种具有装置和电路的装置。 该设备具有多个位线，并且被配置为存储码字。 电路被配置为（i）从设备接收码字，（ii）通过执行小于码字上的全部迭代解码过程的部分来产生综合征，以及（iii）根据综合征产生缺陷图。 地图中的多个比特中的每一个对应于相应的一个比特线。

公开(公告)号：US20150128006A1

公开(公告)日：2015-05-07

申请号：US14101679

申请日：2013-12-10

Applicant: LSI Corporation

Inventor： AbdelHakim S. Alhussien ,  Earl T. Cohen ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1068 ,  G06F11/3037 ,  G06F11/3065 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/3753 ,  H03M13/612 ,  H03M13/6516

Abstract: An apparatus having a device and a circuit is disclosed. The device is configured to convey a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword, (iii) generate a value by counting a number of unsatisfied parity checks in the syndrome and (iv) generate a quality metric of the device according to the value.

Abstract translation: 公开了一种具有装置和电路的装置。 该设备被配置为传送码字。 电路被配置为（i）从设备接收码字，（ii）通过对码字执行小于全部迭代解码过程的部分来生成校验子，（iii）通过计数不满足奇偶校验的数量来生成值 检查综合征和（iv）根据该值产生设备的质量度量。

公开(公告)号：US20140359395A1

公开(公告)日：2014-12-04

申请号：US13911443

申请日：2013-06-06

Applicant: LSI Corporation

Inventor： Jackson L. Ellis ,  Earl T. Cohen ,  Sivakumar Sambandan ,  Jeonghun Kim ,  Stephen D. Hanna

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  G11C29/00

Abstract: A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

Abstract translation: 公开了一种用于保护存储器中的数据的方法。 该方法通常包括步骤（A）至（D）。 步骤（A）将多个逻辑单元中的一个逻辑单元的逻辑地址转换为多个物理单元中相应一个的物理地址。 每个物理单元被配置为存储（i）来自逻辑单元中的相应一个的数据，（ii）各自的纠错信息和（iii）相应的验证信息。 步骤（B）将特定的一个物理单元写入存储器。 步骤（C）从存储器读取特定物理单元的一部分。 该部分包括相应的验证信息。 相应的验证信息包括逻辑地址的指示。 步骤（D）根据该部分中的相应验证信息验证写入。

公开(公告)号：US20140281057A1

公开(公告)日：2014-09-18

申请号：US13864494

申请日：2013-04-17

Applicant: LSI CORPORATION

Inventor： Earl T. Cohen ,  Mark vonGnechten

IPC: G06F5/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F15/173

Abstract: A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs. Each of the processors is associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via respective hardware unit input and output communication FIFOs. Each of the processors is enabled to send messages to others of the processors via respective processor output communication FIFOs. The respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input communication FIFOs.

Abstract translation: 系统包括多个处理器，消息结构和多个硬件单元。 多个处理器中的每一个包括多个通信FIFO，并且具有包括至少一个指令的指令集，以通过多个通信FIFO中的至少一个发送消息。 消息结构通过多个通信FIFO中的至少一些来耦合处理器。 每个处理器与相应的一个或多个硬件单元相关联，并经由相应的硬件单元输入和输出通信FIFO耦合到每个相关联的硬件单元。 每个处理器都能够通过相应的处理器输出通信FIFO将消息发送到处理器的其他处理器。 与每个处理器相关联的各个硬件单元能够经由相应的硬件单元输入通信FIFO向相关联的处理器发送消息。

公开(公告)号：US20140215123A1

公开(公告)日：2014-07-31

申请号：US13750200

申请日：2013-01-25

Applicant: LSI CORPORATION

Inventor： Leonid Baryudin ,  Earl T. Cohen ,  Gordon James Coleman

IPC: G06F12/02

CPC classification number: G06F13/16 ,  G06F12/0246 ,  G06F13/4239

Abstract: The disclosure is directed to a system and method for controlling a non-volatile memory (NVM) device with controller-opaque commands issued by a host. A device controller is configured to receive a command script from a host. The device controller executes one or more commands of the command script including sending one or more operations of the command script to a NVM device in communication with the device controller. The device controller is enabled to provide at least a portion of the one or more operations from the command script to be executed by the NVM device without any embedded knowledge by the device controller of the actions of and/or consequences of the operations, thereby allowing the host to access NVM commands that are not necessarily supported by the device controller.

Abstract translation: 本公开涉及一种用于通过由主机发出的具有控制器不透明命令来控制非易失性存储器（NVM）设备的系统和方法。 设备控制器被配置为从主机接收命令脚本。 设备控制器执行命令脚本的一个或多个命令，包括将命令脚本的一个或多个操作发送到与设备控制器通信的NVM设备。 设备控制器能够从命令脚本中提供要由NVM设备执行的一个或多个操作的至少一部分，而无需设备控制器对操作和/或后果的任何嵌入知识，从而允许 主机访问设备控制器不一定支持的NVM命令。