中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.018 seconds)

    MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION
    1.
    发明申请
    MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION 有权
    软读取操作的无效决策模式的管理

    公开(公告)号：US20140181617A1

    公开(公告)日：2014-06-26

    申请号：US13721739

    申请日：2012-12-20

    Applicant: LSI CORPORATION

    Inventor： Yunxiang Wu ,  Ning Chen ,  Jamal Riani ,  Hakim Alhussien

    IPC: H03M13/05

    CPC classification number: H03M13/612 ,  H03M13/1111 ,  H03M13/3723

    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.

    Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于（i）从查找表检索的值和（ii）索引信号来生成输出信号。 第二电路可以被配置为响应于多个寻呼信号而生成索引信号。 该装置可以在软重试期间管理决策模式。

    FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE
    4.
    发明申请
    FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE 有权
    FLASH MEMORY读取错误恢复与软决策解码

    公开(公告)号：US20140164868A1

    公开(公告)日：2014-06-12

    申请号：US13798864

    申请日：2013-03-13

    Applicant: LSI CORPORATION

    Inventor： Erich F. Haratsch ,  Jeremy Werner ,  Zhengang Chen ,  Earl T. Cohen ,  Yunxiang Wu ,  Ning Chen

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/45 ,  H03M13/6561

    Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

    Abstract translation: 公开了一种具有电路和一个或多个处理器的装置。 电路被配置为从存储器接收码字。 存储器是非易失性的。 码字通常具有一个或多个错误。 处理器被配置为通过重复地解码码字来生成读取数据。 解码包括软判决解码，其使用通过（i）第一过程计算的多个参数，（ii）响应于解码的多个故障使用第一过程收敛的第二过程，以及（iii） 响应于使用第二过程的解码收敛的另一个故障的第三过程。

    METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS
    5.
    发明申请
    METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS 有权
    通过提高错误率变化分配不同页面类型的用户数据和错误校正数据的方法

    公开(公告)号：US20150178149A1

    公开(公告)日：2015-06-25

    申请号：US14173108

    申请日：2014-02-05

    Applicant: LSI Corporation

    Inventor： Yu Cai ,  Ning Chen ,  Yunxiang Wu ,  Erich F. Haratsch ,  Earl T. Cohen ,  Timothy L. Canepa

    IPC: G06F11/10

    CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072

    Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

    Abstract translation: 一种装置包括存储器和控制器。 存储器包括多个存储器件。 每个存储器设备具有多个页面类型。 基于错误率变化对多个页面类型进行分类。 控制器可以被配置为将用户数据和纠错数据写入存储器。 用户数据和纠错数据被组织为超级页面。 超级页面包括多个子页面。 多个子页面被跨越多个存储器件写入，使得使用多个页面类型中的多个页面类型存储多个子页面。

    Method of optimizing solid state drive soft retry voltages
    6.
    发明授权
    Method of optimizing solid state drive soft retry voltages 有权
    优化固态硬盘软重试电压的方法

    公开(公告)号：US09025393B2

    公开(公告)日：2015-05-05

    申请号：US13856179

    申请日：2013-04-03

    Applicant: LSI Corporation

    Inventor： Yunxiang Wu ,  Zhengang Chen ,  YingQuan Wu ,  Ning Chen

    IPC: G11C11/56 ,  G11C29/42 ,  G11C16/00 ,  G11C29/02 ,  G11C29/50

    CPC classification number: G11C11/5642 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

    Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

    Abstract translation: 优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。 该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。 每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。 每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。 该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。

    Lempel-Ziv data compression with shortened hash chains based on repetitive patterns
    7.
    发明授权
    Lempel-Ziv data compression with shortened hash chains based on repetitive patterns 有权
    基于重复模式的Lempel-Ziv数据压缩与缩短的哈希链

    公开(公告)号：US08912932B2

    公开(公告)日：2014-12-16

    申请号：US13803946

    申请日：2013-03-14

    Applicant: LSI Corporation

    Inventor： Ning Chen ,  Robin Sik

    IPC: H03M7/30

    CPC classification number: H03M7/3086

    Abstract: Methods and apparatus are provided for Lempel-Ziv data compression with shortened hash chains based on repetitive multi-byte runs. Data is compressed by processing a sequence of data to identify a repetitive pattern, such as a multi-byte run; and providing indicators associated with the sequence of data of a start position and an end position of the repetitive pattern. The indicators of the start and end positions of the repetitive pattern may comprise, for example, flags associated with the positions. The indicators of the start and end positions of the repetitive pattern are processed to determine a sequence length of the repetitive pattern. In addition, a match can be identified in the sequence of data having a length that is greater than or equal to an offset of s bytes to identify a run comprised of an s-byte sequence.

    Abstract translation: 提供了基于重复多字节运行的具有缩短的散列链的Lempel-Ziv数据压缩的方法和装置。 通过处理数据序列来压缩数据以识别重复模式，例如多字节运行; 并提供与重复模式的开始位置和结束位置的数据序列相关联的指示符。 重复模式的开始和结束位置的指示符可以包括例如与位置相关联的标志。 处理重复图案的开始和结束位置的指示符以确定重复图案的序列长度。 此外，可以在具有大于或等于s字节的偏移的长度的数据序列中识别匹配，以识别由s字节序列组成的运行。

    Method of Optimizing Solid State Drive Soft Retry Voltages
    8.
    发明申请
    Method of Optimizing Solid State Drive Soft Retry Voltages 有权
    优化固态硬盘软重试电压的方法

    公开(公告)号：US20140286102A1

    公开(公告)日：2014-09-25

    申请号：US13856179

    申请日：2013-04-03

    Applicant: LSI CORPORATION

    Inventor： Yunxiang Wu ,  Zhengang Chen ,  YingQuan Wu ,  Ning Chen

    IPC: G11C29/04

    CPC classification number: G11C11/5642 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

    Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

    Abstract translation: 优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。 该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。 每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。 每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。 该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。

    ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY
    9.
    发明申请
    ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY 有权
    非易失性存储器的错误校正代码率管理

    公开(公告)号：US20140164880A1

    公开(公告)日：2014-06-12

    申请号：US13798696

    申请日：2013-03-13

    Applicant: LSI CORPORATION

    Inventor： Zhengang Chen ,  Jeremy Werner ,  Earl T. Cohen ,  Ning Chen ,  AbdelHakim S. Alhussien ,  Erich F. Haratsch

    IPC: G06F11/10

    CPC classification number: G06F11/1012

    Abstract: An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.

    Abstract translation: 示出了具有接口和电路的装置。 该接口耦合到非易失性存储器。 电路被配置为（i）基于与该块相关联的编程/擦除计数，从存储器中的块读取多个码字，（ii）对用于解码码字的迭代次数进行计数，以及（iii）减少一个 用于响应于超过阈值的迭代次数来编程块的纠错编码的码率。

    METHOD TO SHORTEN HASH CHAINS IN LEMPEL-ZIV COMPRESSION OF DATA WITH REPETITIVE SYMBOLS
    10.
    发明申请
    METHOD TO SHORTEN HASH CHAINS IN LEMPEL-ZIV COMPRESSION OF DATA WITH REPETITIVE SYMBOLS 有权
    使用重复符号缩短数据采集的数据中的哈希链的方法

    公开(公告)号：US20140114937A1

    公开(公告)日：2014-04-24

    申请号：US13659036

    申请日：2012-10-24

    Applicant: LSI CORPORATION

    Inventor： Ning Chen

    IPC: G06F7/00 ,  G06F17/30

    CPC classification number: G06F3/0608 ,  G06F3/0638 ,  G06F3/0679 ,  H03M7/3084

    Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a sequence of hash values in a table from a stream of data values with repetitive values, (ii) find two consecutive ones of the hash values in the sequence that have a common value and (iii) create a shortened hash chain by generating a pointer in the table at an intermediate location that corresponds to a second of the two consecutive hash values. The pointer generally points forward in the table to an end location that corresponds to a last of the data values in a run of the data values.

    Abstract translation: 公开了一种具有电路的装置。 电路可以被配置为（i）从具有重复值的数据值流中产生表中的散列值序列，（ii）在序列中找到具有公共值的两个连续的哈希值，并且（iii ）通过在对应于两个连续哈希值中的第二个的中间位置处的表中生成指针来创建缩短的哈希链。 指针通常在表中向前指向与数据值运行中最后一个数据值相对应的结束位置。

Patent Agency Ranking