公开(公告)号：US07490202B2

公开(公告)日：2009-02-10

申请号：US11956112

申请日：2007-12-13

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

公开(公告)号：US20100262735A1

公开(公告)日：2010-10-14

申请号：US12423355

申请日：2009-04-14

申请人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

发明人： Lakshminarayana Baba Arimilli ,  Brian Mitchell Bass ,  David Wayne Cummings ,  Bernard Charles Drerup ,  Guy Lynn Guthrie ,  Ronald Nick Kalla ,  Hugh Shen ,  Michael Steven Siegel ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F13/14 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1458 ,  G06F9/30047 ,  G06F9/30087 ,  G06F12/0893

摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls.

摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令（通过系统总线）的从设备处理特定请求类型命令。

公开(公告)号：US07305523B2

公开(公告)日：2007-12-04

申请号：US11056673

申请日：2005-02-12

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

公开(公告)号：US07284102B2

公开(公告)日：2007-10-16

申请号：US11054450

申请日：2005-02-09

申请人： Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/0817

摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.

摘要翻译： 一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。 当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。 响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。 响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功 通过RC调度逻辑调度到RC机器。

公开(公告)号：US07228385B2

公开(公告)日：2007-06-05

申请号：US10965113

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0855

摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器 在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。 定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行 加载预备操作先前绑定到的高级缓存。

公开(公告)号：US07783834B2

公开(公告)日：2010-08-24

申请号：US11947742

申请日：2007-11-29

申请人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

发明人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0822 ,  G06F12/0824

摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

摘要翻译： 缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行 。 优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。 在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中 并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。 可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。 给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。 例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个 四个周期。

公开(公告)号：US06487637B1

公开(公告)日：2002-11-26

申请号：US09364408

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1300

CPC分类号： G06F9/30047 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0897

摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. Further branch predictions or stream associations that were made based on an earlier speculative choice are linked by using a tag pool which assigns a bit fields in the tag pool entries to the level of speculation depth. Each entry shares in common the bit field values associated with earlier branches or stream associations. When a branch or stream predicted entry is no longer needed, that entry can be cancelled and all entries that were to be loaded dependent on that entry can likewise be cancelled by walking through all entries sharing the bit fields corresponding to the speculation depth of the cancelled entry and tagging those entries as invalid.

摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 通过使用将标签池条目中的位字段分配给投机深度的标签池来链接根据较早的推测选择进行的进一步分支预测或流关联。 每个条目共享与早期分支或流关联相关联的比特字段值。 当不再需要分支或流预测条目时，可以取消该条目，并且可以通过遍历与所取消的投机深度相对应的比特字段的所有条目，来取消根据该条目加载的所有条目 输入并标记这些条目为无效。

公开(公告)号：US06438656B1

公开(公告)日：2002-08-20

申请号：US09364574

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0862 ,  G06F12/0897

摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. After a predetermined number of cycles has elapsed, the speculative load request is cancelled if the request has not already been completed.

摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 在经过预定数量的周期之后，如果请求尚未完成，则推测加载请求被取消。

公开(公告)号：US06418516B1

公开(公告)日：2002-07-09

申请号：US09364409

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F1208

CPC分类号： G06F9/30047 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0862 ,  G06F12/0897

摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions and treats instructions in a different manner when they are loaded speculatively. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. The load requests are sent to the lower level cache when the upper level cache does not contain the value required by the load. If a speculative request is for an instruction which is likewise not present in the lower level cache, that request is ignored, keeping both the lower level and upper level caches free of speculative values that are infrequently used. If the value is present in the lower level cache, it is loaded into the upper level cache. If a speculative request is for operand data, the value is loaded only into the lower level cache if it is not already present, keeping the upper level cache free of speculative operand data.

摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值，并且当它们被推测地加载时以不同的方式对待指令。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 当高级缓存不包含负载所需的值时，负载请求将发送到较低级别的缓存。 如果对低级缓存中同样不存在的指令进行推测性请求，则忽略该请求，同时保持较低级别和上级缓存都不会被不经常使用的推测值。 如果该值存在于较低级缓存中，则将其加载到上级缓存中。 如果对于操作数数据是推测性请求，则该值仅在尚未存在的情况下被加载到较低级别的高速缓存中，保持高级缓存没有推测操作数数据。

公开(公告)号：US07366841B2

公开(公告)日：2008-04-29

申请号：US11054930

申请日：2005-02-10

申请人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

发明人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0822 ,  G06F12/0824

摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

摘要翻译： 缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行 。 优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。 在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中 并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。 可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。 给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。 例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个 四个周期。