公开(公告)号：US10153026B2

公开(公告)日：2018-12-11

申请号：US15858831

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  G11C11/56 ,  H01L27/11507 ,  G11C14/00 ,  H01L27/11502

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

公开(公告)号：US09928894B2

公开(公告)日：2018-03-27

申请号：US15438462

申请日：2017-02-21

Applicant: Micron Technology, Inc.

Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  G11C14/00 ,  G11C11/56 ,  H01L27/11507 ,  H01L27/11502

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/5657 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

公开(公告)号：US20180005682A1

公开(公告)日：2018-01-04

申请号：US15438462

申请日：2017-02-21

Applicant: Micron Technology, Inc.

Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  G11C14/00 ,  H01L27/11507 ,  G11C11/56 ,  H01L27/11502

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/5657 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

公开(公告)号：US20160172031A1

公开(公告)日：2016-06-16

申请号：US15050248

申请日：2016-02-22

Applicant: Micron Technology, Inc.

Inventor： Emiliano Faraoni ,  Scott E. Sills ,  Alessandro Calderoni ,  Adam Johnson

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

公开(公告)号：US09230685B2

公开(公告)日：2016-01-05

申请号：US13658519

申请日：2012-10-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan Strand ,  Adam Johnson ,  Xiaonan Chen ,  D. V. Nirmal Ramaswamy

IPC: G11C11/00 ,  G11C29/08 ,  G11C29/50 ,  G11C13/00 ,  G11C29/04

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0064 ,  G11C29/08 ,  G11C29/50008 ,  G11C2013/0073 ,  G11C2029/0409 ,  G11C2029/5006

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract translation: 描述了存储器编程方法和存储器系统。 一个示例性存储器编程方法包括：首先将第一信号施加到存储器单元以尝试将存储器单元编程到期望状态，其中第一信号对应于期望状态，在第一次施加之后，确定存储器单元不能放置 在所需状态下，在确定之后，向存储单元施加第二信号，其中第二信号对应于与期望状态不同的另一状态，并且在第二次施加之后，第三信号施加到存储单元 将存储器单元编程到所需状态，其中第三信号对应于期望状态。 描述附加的方法和装置。